RAiO RA8806 - Display Future

RAiO 

RA8806 

Two Layers 

Character/Graphic 

LCD Controller 

Specification 

Version 1.3 

August 24, 2009 

RAiO Technology Inc. 

©Copyright RAiO Technology Inc. 2008, 2009 

RAiO TECHNOLOGY INC. 1/193 www.raio.com.tw

Version 1.3 


Two Layers Character/Graphic LCD Controller 

Update History 

Version Date Description 

1.0 March 25, 2008 Preliminary Version 

1.1 June 20, 2008 

1.2 March 2, 2009 

1.3 August 24, 2009 

1. 6-4-3 Touch panel sampling time reference table 

2. Add Section 6-15 Eliminating Flicker Mode 

3. Update Table 8-2 DC characteristic 

4. Add Section 8-3 for RA8806 driver I/F timing chart 

5. Update font table of Appendix D and Appendix E 

1. Add the description of Japanese Kanji font version of RA8806-J. 

2. Update Figure 6-38、Figure 6-39 PWM Reference Circuits 

3. Update the Section 6-10-1-3 for the usage of Chinese font and 

Japanese Kanji font. 

1. Update Table 5-2 Register Table. 

2. Upddate Section 6-5 Key Scan for Key Pressed Number. 

3. Update Table 8-2 DC Characteristic. 


Version 1.3 



Chapter Content Page 

1. General Description ......................................................................................6 

2. Feature ...........................................................................................................6 

3. Block Diagram ...............................................................................................7 

4. Pin Definition .................................................................................................8 

4-1 MPU Interface .............................................................................................................8 

4-2 Clock Interface............................................................................................................8 

4-3 Peripheral Interface....................................................................................................9 

4-4 LCD Driver Interface.................................................................................................10 

4-5 Power ........................................................................................................................10 

5. Register Description ...................................................................................11 

5-1 Register List Table ...................................................................................................11 

5-2 Register Description ................................................................................................13 

6. Function Description ..................................................................................27 

6-1 MPU Interface ...........................................................................................................27 

6-1-1 MPU Type ................................................................................................................................... 27 

6-1-2 Command Write ......................................................................................................................... 30 

6-1-3 Memory Write/Read ................................................................................................................... 31 

6-1-4 Status Read................................................................................................................................ 31 

6-2 Driver Interface.........................................................................................................32 

6-2-1 Display Resolution .................................................................................................................... 35 

6-2-2 Display Window and Active Window....................................................................................... 35 

6-2-3 Com/Seg Scan Direction........................................................................................................... 38 

6-2-4 Idle Time Counter (ITCR) .......................................................................................................... 38 

6-3 Display Data RAM (DDRAM) ....................................................................................40 

6-3-1 Display Layer and Display Mode Selection ............................................................................ 40 

6-3-2 Access Memory Selection ........................................................................................................ 40 

6-4 Touch Panel..............................................................................................................41 

6-4-1 Auto Mode .................................................................................................................................. 43 

6-4-2 Manual Mode.............................................................................................................................. 45 

6-4-2-1 External Interrupt Mode .................................................................................................... 45 

6-4-2-2 Polling Mode ..................................................................................................................... 48 

6-4-3 Touch Panel Sampling Time Reference Table ....................................................................... 51 

6-5 Key-Scan...................................................................................................................52 

6-6 Clock and Reset .......................................................................................................59 

6-6-1 OSC Circuit................................................................................................................................. 59 

6-6-2 External Clock............................................................................................................................ 59 

6-6-3 Reset ........................................................................................................................................... 60 

6-7 Power ........................................................................................................................61 

6-7-1 Power Architecture ................................................................................................................... 61 

6-7-2 3V Application Circuit ............................................................................................................... 61 

6-7-3 5V Application Circuit ............................................................................................................... 62 


Version 1.3 



6-7-4 Sleep Mode................................................................................................................................. 63 

6-8 Interrupt and Busy ...................................................................................................64 

6-8-1 Interrupt...................................................................................................................................... 64 

6-8-2 Busy ............................................................................................................................................ 65 

6-9 PWM ..........................................................................................................................68 

6-10 Display Function.....................................................................................................70 

6-10-1 Character/Graphic Mode........................................................................................................... 70 

6-10-1-1 Graphic Display ................................................................................................................ 70 

6-10-1-2 Half Size Font ................................................................................................................... 71 

6-10-1-3 Full Size Font.................................................................................................................... 72 

6-10-1-4 Bold and Inverse............................................................................................................... 75 

6-10-1-5 Two Layer Display ............................................................................................................ 76 

6-10-1-6 Line Gap ........................................................................................................................... 77 

6-10-2 Gray Scale Display .................................................................................................................... 77 

6-10-3 Font Size Adjustment and Font Write-Time............................................................................ 80 

6-10-4 Font Vertical Display ................................................................................................................. 82 

6-11 User-Defined Font ..................................................................................................84 

6-11-1 Create Font in CGRAM.............................................................................................................. 84 

6-11-2 Create Font in DDRAM.............................................................................................................. 88 

6-11-3 Create Symbol............................................................................................................................ 92 

6-12 Scroll Function .......................................................................................................94 

6-12-1 Horizontal Scrolling................................................................................................................... 94 

6-12-2 Vertical Scrolling ....................................................................................................................... 96 

6-13 Cursor......................................................................................................................97 

6-13-1 Cursor Position and Shift ......................................................................................................... 97 

6-13-2 Full Alignment............................................................................................................................ 97 

6-13-3 Cursor Blinking........................................................................................................................ 100 

6-13-4 Cursor Width and Height ........................................................................................................ 100 

6-14 Extension Mode for Display.................................................................................101 

6-15 Eliminating Flicker Mode .....................................................................................104 

7. Package Information .................................................................................108 

7-1 Bonding Pad ...........................................................................................................108 

7-2 Pad X/Y Coordinate ................................................................................................109 

7-3 Pin Assignment ......................................................................................................110 

7-4 Package Dimension ...............................................................................................111 

7-5 Part Number............................................................................................................115 

8. Electrical Characteristic ...........................................................................116 

8-1 Absolute Maximum Ratings ..................................................................................116 

8-2 DC Characteristic ...................................................................................................117 

8-3 Timing Characteristic Wavaform ..........................................................................118 

Appendix A . Application Circuit..................................................................119 

Appendix B . Frame Rate Table....................................................................120 

Appendix C . Font Table - ASCII...................................................................123 

Appendix D . Font Table - GB Code.............................................................131 


Version 1.3 



Appendix E . Font Table - BIG-5 Code.........................................................153 

Appendix F . Font Table - JIS Code.............................................................184 


Version 1.3 



1. General Description 

RA8806 is a LCD controller for Dot-Matrix type STN-LCD which supports both character and graphic mode 

display. The RA8806 has built-in two Display Data RAM(DDRAM) for two layers display, and has an 

embedded font ROM which is capable of displaying the full-size(16x16 pixels) traditional Chinese font(BIG5, 

13973 characters) or simplified Chinese font(GB, 9216 characters). RA8806-J is one controller in this series 

that consisting of Kanji and Hiragana according to the JIS standard Level-1 & 2 Kanji font (6,355 characters). 

RA8806 also contains 4x256 embedded half-size (8x16 pixels) characters that can display ISO8859-1 ~ 4(or 

called Latin-1 ~ 4) alphabets using at most of English speaking and Europe countries. 

RA8806 supports 8080/6800 MPU protocol interface, which is capable of switching the interface with 4-bits 

or 8-bits data bus. For LCD driver interface, it can be set to 4-bits or 8-bits data bus. The maximum 

resolution of RA8806 is 320x240 pixels in normal mode, and 640x240 or 320x480 pixels in extension mode. 

By using the font rotation mode, which can implement the “vertical” font display. The embedded intelligence 

touch panel controller provides the 4-wires resistance-type Touch Panel interface. The PWM output 

provides an easy contrast or back-light control method for LCD panel. RA8806 also provides a 4x8(32 keys) 

or 8x8(64 keys) powerful and smart Key-Scan interface includes long-key function. The flexible interrupt and 

polling mechanism can make it easy to control touch panel, key-scan and power mode functions. Also it can 

greatly reduce the MPU loading. The embedded 512Byte character generation RAM (CGRAM) allows user 

to build maximum 16 full-size or 32 half-size fonts. Even with the single layer display, the other unused layer 

can be used as CGRAM too. In this setting, the amazing 300 full-size and 600 half-size user created fonts or 

symbols are supported. 

In addition, RA8806 supports 4-gray-scale display in FRC mode. The bit-arrangement is compatible for most 

gray level picture and easy to program. RA8806 also includes many useful functions, like area scroll, font 

inverse, font bold, font enlargement, memory clear function and so on. An innovative mechanism of “noflicker” 

mode is provided in RA8806. It’s effective for removing the “flicker” in frequently display data 

Read/Write. User can easily improve the display quality by RA8806. 

RA8806 is a powerful and flexible LCD controller. It provides the total solution for the middle-size mono LCD 

controller. User can save large amount of time for system development and the cost of hardware system. 

2. Feature 

Support text and graphics mode. 

Maximum resolution: 320x240 with 2-Layers 

overlay display (AND, OR, NOR and XOR). 

Extension Mode: 640x240 or 320x480 with 

single layer. 

Support 4/8-bits of 6800/8080 MPU interface 

and 4/8-bits driver interface. 

Built-In smart 8x8 or 4x8 key-scan circuit with 

programmable long key function. 

Support horizontal and vertical area scrolling 

Built-In GB/BIG5 and ASCII font ROM. 

Support 90°, 180°, 270° font and display 

rotation. 

Support font enlargement(x1 ~ x4 in 

Horizontal and Vertical direction) 

Built-In 512Byte CGRAM for user-created 

font: 

_ Half-size: 8x16 

_ Full-size: 16x16 

Un-used DDRAM could be used as a 

CGRAM of 300 full-size or 600 half-size 

characters. 

Flexible interrupt/polling mechanism for touch 

panel, key-scan and power mode 

programming. 

Support font alignment function. 

Support 4-gray-scale display (FRC mode). 

Support bold font and row-row interval setting 

Built-In smart resister type touch panel 

controller. 

Built-In PWM for contrast or back-light control 

Power mode to reduce power consumption. 

Clock source: 4M ~ 12MHz crystal or external 

clock 

Built-In a 5V-to-3V DC/DC converter 

Power supply: 2.4V ~ 5.5V 

Package: Die, LQFP-100, TQFP-80 Pins 


Version 1.3 



3. Block Diagram 

Figure 3-1 is the internal block diagram of RA8806. The RA8806 consists of two Display Data RAM, Font 

ROM, Register Block, Analog to Digital Converter (ADC), Pulse Width Modulation (PWM), LCD driver 

interface and microprocessor interface. Figure 3-2 is the system block for application of RA8806. 

KIN[7:0] 

KOUT[7:0] 

PWM_OUT 

Smart 

Key-Scan 

Controller 

PWM 

Controller 

Display Data RAM 

(9.6KByte x 2) 

DDRAM1 

DDRAM2 

Registers 

Display 

Timing 

Generator 

LP 

FR 

YD 

ZDOFF 

XCK 

LD[7:0] 

XG 

XD 

Oscillator 

512KByte 

Font 

ROM 

512Byte 

CGRAM 

MCU Interface 

System Configure 

Touch Panel 

Controller 

X1 

X2 

Y1 

Y2 

ZCS1 

CS2 

ZWR 

ZRD 

RS 

INT 

BUSY 

DATA[7:0] 

ZRST 

MI 

DW 

DB 

CLK_OUT 

Figure 3-1 : RA8806 Block Diagram 

MPU 

LCD Driver 

LCD Panel 

8x8 

Key Pad 


Booster 

(Contrast Adj.) 

LCD Driver 

Touch 

H/W 

Set Up 

Panel 

X’tal 

Figure 3-2 : RA8806 System Block Diagram 


Version 1.3 



4. Pin Definition 

4-1 MPU Interface 

Pin Name I/O Description 

DATA[7:0] I/O 

Data Bus 

These are data bus for data transfer between MPU and RA8806. 

The high nibble DATA[7:4] is output and should keep floating when 4-bits 

data bus mode is used. 

Enable/Read Enable 

ZRD 

When MPU interface(I/F) is 8080 series, this pin (ZRD) is used as data read, 

I 

(EN) 

active low. 

When MPU I/F is 6800 series, this pin (EN) is used as Enable, active high. 

Write/Read-Write 

When MPU I/F is 8080 series, this pin (ZWR) is used as data write, active 

ZWR 

I low. 

(ZRW) 

When MPU I/F is 6800 series, this pin(ZRW) is used as data read/write 

control. Active high for read and active low for write. 

Command / Data Select Input 

The pin is used to select command/data cycle. RS = 0, data Read/Write 

cycle is selected. RS = 1, status read/command write cycle is selected. 

In 8080 interface, usually it connects to “A0” address pin. 

RS 

ZCS1 

CS2 

INT 

BUSY 

I 

I 

O 

O 

RS ZWR ZRD Access Cycle 

0 0 1 Data Write 

0 1 0 Data Read 

1 0 1 CMD Write 

1 1 0 Status Read 

Chip Select Input 

The MPU interface of RA8806 is active only when ZCS1 is low and CS2 is 

high. 

Interrupt Signal Output 

The interrupt output for MPU to indicate the status of RA8806. It could be 

setup active high or low. 

Busy Signal Output 

This is a busy output to indicate the RA8806 is in busy state. It could be set 

to active high or active low by register. The RA8806 can’t access MPU cycle 

when BUSY pin is active. 

It could be used for MPU to poll busy status by connecting it to I/O port. 

4-2 Clock Interface 


XG 

I 

X’tal Input 

In internal clock mode, this pin connects to external X’tal(4M ~ 12MHz). 

In external clock mode, it connects to external clock. 

XD 

O 

X’tal Output 

This pin connects to external X’tal(4M ~ 12MHz). In external clock mode, it 

keeps floating. 


Version 1.3 



4-3 Peripheral Interface 


ZRST 

I 

Reset Signal Input 

This active-low input performs a hardware reset on the RA8806. It is a 

Schmitt-trigger input with pull-up resistor for enhanced noise immunity; 

however, care should be taken to ensure that it is not triggered if the 

supply voltage is lowered. 

X1 

I 

Touch Panel Input 

The left analog input pin(XL) of 4-wires touch panel. 

X2 

I 


The right analog input pin(XR) of 4-wires touch panel. 

Y1 

I 


The top analog input pin(YU) of 4-wires touch panel. 

If user want to use Touch Panel function, please add a 39K~51Kohm 

external pull-up resistor on this pin. 

Y2 

I 


The bottom analog input pin(YD) of 4-wires touch panel. 

PWM_OUT 

KIN[7:0] 

KOUT[7:0] 

CLK_OUT 

DW 

MI 

DB 

O 

I 

O 

O 

I 

I 

I 

PWM Output Signal 

This output signal is used to control back-light module or booster circuit. 

Key Pad Input 

These pins are keypad inputs with pull-up resistors. For un-used input, 

please keep floating. 

Key Pad Output 

These pins are keypad outputs. For un-used pin, please keep floating. 

Clock Output 

This is a multi-function output pin that depending on the value of register 

REG[01h] Bit-6. 

REG[01h] Bit-6 = 0: The pin is the output of internal system clock. 

REG[01h] Bit-6 = 1: The pin indicate the SLEEP state of Status 

Register(0: Normal Mode, 1: Sleep Mode). 

LCD Driver Data Bus Select 

This pin is used to select data bus of LCD driver is 8-bits or 4-bits: 

0 : LCD driver data bus is 4-bits, LD[3:0] is used. 

1 : LCD driver data bus is 8-bits, LD[7:0] is used. 

When 4-bits data bus is used, LD[7:4] need to keep floating. RA8806T1N 

does not support this function, its LCD driver data bus is fix 4-bits. 

MPU Type Select 

This pin is used to select MPU interface protocol: 

0 : Intel 8080 series MPU interface. 

1 : Motorola 6800 series MPU interface. 

8080/6800 MPU Data Bus Select 

This pin is used to select data bus width. 

0 : 4-bits MPU I/F, DATA[3:0] is used. 

1 : 8-bits MPU I/F, DATA[7:0] is used. 

When 4-bits data bus is used, DATA[7:4] need to keep floating. 


Version 1.3 



4-4 LCD Driver Interface 


YD 

O 

Start Signal of LCD Per Frame 

YD is the reset pulse for the COM driver, it’s active during the last COM 

period of each frame and latched by LP signal. 

FR 

O 

LCD AC Wave Output 

This signal controls the Level Shift of LCD driver. Normally it works as 

VDD/GND interlacing to prevent the liquid cystal polarization. 

LP 

O 

LCD Common Latch 

LP is the latch pulse for the shift register of SEG driver to SEG output. It is 

also used as COM driver shift clock. 

XCK 

O 

LCD Clock 

XCK is the latch pulse of the LCD driver data(LD[7:0]) for SEG driver. The 

falling edge of XCK will latch the LD[7:0] (or LD[3:0] for 4-bits driver) to the 

shift register. 

ZDOFF O 

LCD Display Off 

This signal is used to control the LCD Display On or Off. 

0 : Display off. 

1 : Display on. 

LD[7:0] O 

LCD Driver Data Bus 

When 8-bits LCD driver IC is used. LD[7:0] are connected to LCD driver 

data bus. When 4-bits driver is used, LD[3:0] are connected to LCD driver 

data bus and LD[7:4] keep floating. 

RA8806T1N supports LD[3:0] only. 

4-5 Power 


VDDH P 

5V Power 

This is the source power for DC to DC converter. In 5V power application, 

it is connected to 5V. If 3V application is used, then keep this pin floating. 

VDD 

P 

3V Power (Users need to add 1µF and 0.1µF capacitors in parallel at 

VDD to increase power stability) 

If the pin VDDH connects to 5V power then the pin will driving 3V power, 

and must add an external 1uF capacitor to GND. If 3V application is used, 

then connecting this pin to external 3V power directly. 

VDDP P 

Power for I/O Buffer 

VDDP can be 3V or 5V. 

AVDD P 

Analog Power for ADC Touch Panel Controller 

AVDD can be 3V or 5V. 

GND 

GNDP 

P Ground 

AGND P 

Analog Ground for ADC Touch Panel Controller 

Connect this pin to 0V earth ground(GND). 

TESTMD I 

Test Mode 

This pin is used for test only. It has internal pull-low and need to keep 

floating. 

TESTI 

I 

Test Pin 

The pin is used for test function, It has internal pull-low and need to keep 

floating. 


Version 1.3 



5. Register Description 

5-1 Register List Table 

Table 5-1 : Cycle List Table 

CYC_NAME RS ZWR Description 

CMD 1 0 Command write cycle, for writting register number(REG#) 

STATUS 1 1 Status read cycle, using to check Interrupt or Sleep status. 

DATW 0 0 Data write cycle, using to write register data or memory data. 

DATR 0 1 Data read cycle, using to read register data or memory data. 

Table 5-2 : Register Table 

REG# Name D7 D6 D5 D4 D3 D2 D1 D0 Default 

-- STATUS MBUSY SBUSY SLEEP WAKE_STS KS_STS TP_STS -- 

00h WLCR PWR LINEAR SRST -- TEXT_MD ZDOFF GBLK GINV 00h 

01h MISC 

NO_ 

BUSY_ 

CLKO_SEL 

FLICKER 

LEV 

INT_LEV XCK_SEL1 XCK_SEL0 SDIR CDIR 04h 

03h ADSR SCR_PEND -- -- -- BIT_INV SCR_DIR SCR_HV SCR_EN 00h 

0Fh INTR -- WAKI_EN KEYI_EN TPI_EN TP_ACT WAK_STS KEY_STS TP_STS 00h 

10h WCCR CUR_INC FULL_OFS BIT_REV BOLD T90DEG CUR_EN CUR_BLK --- 00h 

11h CHWI CURH3 CURH2 CURH1 CURH0 ROWH3 ROWH 2 ROWH 1 ROWH 0 00h 

12h MAMR CUR_HV DISPMD2 DISPMD1 DISPMD0 L_MIX1 L_MIX 0 MW_MD1 MW_MD0 11h 

20h AWRR -- -- AWR5 AWR4 AWR3 AWR2 AWR1 AWR0 27h 

21h DWWR -- -- DWW5 DWW 4 DWW 3 DWW 2 DWW 1 DWW 0 27h 

30h AWBR AWB7 AWB6 AWB5 AWB4 AWB3 AWB2 AWB1 AWB0 EFh 

31h DWHR DWH7 DWH6 DWH5 DWH4 DWH3 DWH2 DWH1 DWH0 EFh 

40h AWLR -- -- AWL5 AWL4 AWL3 AWL2 AWL1 AWL0 00h 

50h AWTR AWT7 AWT6 AWT5 AWT4 AWT3 AWT2 AWT1 AWT0 00h 

60h CURX -- -- CURX5 CURX4 CURX3 CURX2 CURX1 CURX0 00h 

61h BGSG -- -- BGSG5 BGSG4 BGSG3 BGSG2 BGSG1 BGSG0 00h 

62h EDSG EDSG7 EDSG6 EDSG5 EDSG4 EDSG3 EDSG2 EDSG1 EDSG0 00h 

70h CURY CURY7 CURY6 CURY5 CURY4 CURY3 CURY2 CURY1 CURY0 00h 

71h BGCM BGCM7 BGCM6 BGCM5 BGCM4 BGCM3 BGCM2 BGCM1 BGCM0 00h 

72h EDCM EDCM7 EDCM6 EDCM5 EDCM4 EDCM3 EDCM2 EDCM1 EDCM0 00h 

80h BTMR BLKT7 BLKT6 BLKT5 BLKT4 BLKT3 BLKT2 BLKT1 BLKT0 00h 

90h ITCR ITC7 ITC6 ITC5 ITC4 ITC3 ITC2 ITC1 ITC0 00h 

A0h KSCR1 KEY_EN KEY4X8 KSAMP1 KSAMP0 LKEY_EN KF2 KF1 KF0 00h 

A1h KSCR2 KWAK_EN -- -- -- LKEY_T1 LKEY_T0 KEYNO1 KEYNO0 00h 

A2h KSDR0 KSD07 KSD06 KSD05 KSD04 KSD03 KSD02 KSD01 KSD00 FFh 



B0h MWCR MWD7 MWD6 MWD5 MWD4 MWD3 MWD2 MWD1 MWD0 -- 

B1h MRCR MRD7 MRD6 MRD5 MRD4 MRD3 MRD2 MRD1 MRD0 -- 


Version 1.3 



(Continued) 

REG# Name D7 D6 D5 D4 D3 D2 D1 D0 Default 

C0h TPCR1 TP_EN TP_SMP2 TP_SMP1 TP_SMP0 TPWAK 

_EN 

ACLK2 ACLK1 ACLK0 00h 

C1h TPXR TPX9 TPX8 TPX7 TPX6 TPX5 TPX4 TPX3 TPX2 00h 

C2h TPYR TPY9 TPY8 TPY7 TPY6 TPY5 TPY4 TPY3 TPY2 00h 

C3h TPZR -- -- -- -- TPY1 TPY0 TPX1 TPX0 00h 

C4h TPCR2 MTP_MD -- -- -- -- -- MTP_PH1 MTP_PH2 00h 

D0h PCR PWM_EN PWM_DIS_ 

LEV 

-- -- PCLK_R3 PCLK_R2 PCLK_R1 PCLK_R0 00h 

D1h PDCR PDUTY7 PDUTY6 PDUTY5 PDUTY4 PDUTY3 PDUTY2 PDUTY1 PDUTY0 00h 

E0h PNTR PND7 PND6 PND5 PND4 PND3 PND2 PND1 PND0 00h 

F0h FNCR ISO8859_E 

N 

-- -- -- MCLR ASC ASC_SEL1 ASC_SEL0 00h 

F1h FVHT FH1 FH0 FV1 FV0 -- -- -- -- 00h 


Version 1.3 



5-2 Register Description 

STATUS Register (RS = 1, ZWR = 1) 

Bit Description Access 

7 

Memory Write Busy Flag 

0 : Not busy. 

1 : Busy, when font write or memory clear cycle is running, the busy 

R 

flag = 1. 

6 

SCAN_BUSY 

0 : Not busy. 

1 : When driver scan logic is not idle(i.e. XCK is active), SCAN_BUSY 

R 

= 1. 

5 

SLEEP 

0 : Normal mode. 

R 

1 : Sleep mode. 

4-3 NA R 

2 

Wakeup Status bit 

(The same with REG[0Fh] Bit-2.) 

R 

1 

0 

KS Status bit 


TP Status bit 


R 

R 

REG [00h] Whole Chip LCD Controller Register (WLCR) 

Bit Description Default Access 

7 

Power Mode 

0 : Normal Mode. All of the functions of RA8806 are available in this 

mode. 

1 : Sleep Mode. When RA8806 is in Sleep mode, all of functions enter 

0 R/W 

off mode, except the wake-up trigger block. If wake-up event 

occurred, RA8806 would wake-up and return to Normal mode. 

6 

Linear Decode mode 

This bit is used to define the Font ROM address mapping rule. The 

standard product is set to 0. And 1 for special application that when 

user a want to create a new Mask Code. 

0 R/W 

0 : BIG5/GB ROM mapping rule. 

1 : User-defined ROM mapping rule. 

5 

Software Reset 

0 : Normal Operation. 

1 : Reset all registers except the contents of Display Data RAM (Only 0 R/W 

work at Normal mode). When this bit set to “1”, the next MPU 

cycle for RA8806 have to wait 3 clocks at least. 

4 Reserved 0 R 

3 

Text Mode Selection 

0 : Graphical Mode. The written data will be treated as a bit-map 

pattern. 

1 : Text Mode. The written data will be treated as an ASCII, BIG5 or 

GB code. 

0 R/W 


Version 1.3 



2 

1 

0 

Set Display On/Off Selection 

The bit is used to control LCD Driver Interface signal – “DISP_OFF”. 

0 : DISP_OFF pin output low(Display Off). 

1 : DISP_OFF pin output high(Display On). 

Blink Mode Selection 

0 : Normal Display. 

1 : Blink Full Screen. The blink time is set by register BTMR. 

Inverse Mode Selection 

0 : Normal Display. 

1 : Inverse Full Screen. It will cause the display inversed. 

0 R/W 

0 R/W 

0 R/W 

REG [01h] Misc. Register (MISC) 


7 

Eliminating Flicker 

1 : Eliminating flicker mode, scan will auto-pending when busy. 

0 R/W 

0 : Normal mode. 

6 

Clock Output (Pin CLK_OUT) Control 

1 : The pin “CLK_OUT” indicates the SLEEP state of Status Register(0: 

Normal Mode, 1: Sleep Mode). 

0 R/W 

0 : The pin “CLK_OUT” is the output of Internal system clock. 

5 

Busy Polarity (for “BUSY” pin) 

1 : Set Active High. 

0 R/W 

0 : Set Active Low. 

4 

Interrupt Polarity (for “INT” pin) 

1 : Set Active High. 

0 : Set Active Low. 

0 R/W 

Driver Clock Selection 

These two bits are used to select the clock frequency of XCK. 

3-2 

1 

0 

0 0 : XCK = CLK/8 

0 1 : XCK = CLK/4 (Default) 

1 0 : XCK = CLK/2 

1 1 : XCK = CLK 

The “CLK” means system clock. 

SEG Scan Direction(SDIR) 

0 : SEG order is 0 ~ 319. 

1 : SEG order is 319 ~ 0. 

COM Scan Direction(CDIR) 

0 : COM order 0 ~ 239. 

1 : COM order 239 ~ 0. 

01 R/W 

0 R/W 

0 R/W 

REG [03h] Advance Display Setup Register (ADSR) 


7 Scroll Function Pending 

1 : Scroll function pending 

0 : Scroll function keep active 

0 R/W 

Note: When SCR_HV(Bit-1) and SCR_EN(Bit-0) are changed, the 

function does not support. 

6-4 Reserved 000 R 


Version 1.3 



3 

2 

BIT_ORDER(Set driver data output bit order) 

1 : Inverse driver output data order(Bit-7 to Bit-0, Bit-6 to Bit-1 and so 

on) 

0 : Normal Mode 

SCR_DIR(Scroll Direction) 

When SCR_HV = 0(Horizontal Scroll) 

0 : Left Right. 

1 : Right Left. 

When SCR_HV = 1(Vertical Scroll) 

0 : Top Bottom. 

1 : Bottom Top. 

1 SCR_HV(Scroll Horizontal/Vertical) 

0 : Segment Scrolling(Horizontal). 

1 : Common Scrolling(Vertical). 

SCR_EN(Scroll Enable) 

0 1 : Scroll function enable. 

0 : Scroll function disable. 

0 R/W 

0 R/W 

0 R/W 

0 R/W 

REG [0Fh] Interrupt Setup and Status Register (INTR) 



6 

Wakeup Interrupt Mask 

1 : Enable wake-up Interrupt. 

0 R/W 

0 : Disable wake-up Interrupt. 

5 

Key-Scan Interrupt Mask 

1 : Enable Key-Scan Interrupt. 

0 R/W 

0 : Disable Key-Scan Interrupt. 

4 

Touch Panel Interrupt Mask 

1 : Generate interrupt output if touch panel was detected. 

0 R/W 

0 : Don’t generate interrupt output if touch panel was detected. 

3 

Touch Panel Event(Only activate in TP Manual mode) 

1 : Touch panel is touched. 

0 R 

0 : Touch panel is not touched. 

2 

Wakeup Interrupt Status bit 

1 : Interrupt that indicate wake-up event happen from Sleep mode. 

0 : No wake-up interrupt happen. 

0 R/W 

User must write “0” to clear the Status bit. 

1 

Key-Scan Interrupt Status bit 

1 : Key-Scan Detects Key Events. 

0 : Key-Scan doesn’t Detect Key Events. 


0 R/W 

Ps:There are three kinds of Key Events:Key Pressing、Long Key and 

Key Release. 

0 

Touch Panel Detect Status bit 

1 : Touch Panel Touched. 

0 : Touch Panel Untouched. 


0 R/W 


Version 1.3 



REG [10h] Whole Chip Cursor Control Register (WCCR) 


7 

CUR_INC (Auto Increase Cursor Position in Reading/Writing DDRAM 

Operation.) 

1 : Disable. 

0 R/W 

0 : Enable(Auto Increase). 

6 

FULL_OFS (Full-size and Half-size Character Alignment) 

1 : Enable, in Full-size and Half-size character mixed mode. Chinese 

always start at full-size alignment. 

0 R/W 

0 : Disable. 

5 

Reversed Data Write mode 

0 : Store Current Data to DDRAM Directly. 

1 : Store Current Data to DDRAM Inversely.(i.e. 01101101 

0 R/W 

10010010) 

4 

Bold Font (Character Mode Only) 

1 : Bold Font 

0 R/W 

0 : Normal Font 

3 

Font Rotate mode(T90DEG) 

1 : Font rotates 90 degree. (See Section 6-10-4 for detail) 

0 R/W 

0 : Normal font. 

2 

Cursor Display 

1 : Set Cursor Display On. 

0 R/W 

0 : Set Cursor Display Off. 

1 

Cursor Blinking 

1 : Blink Cursor. The blink time is determined by register BTMR. 

0 R/W 

0 : Normal. 


REG [11h] Cursor Height and Word Interval Register (CHWI) 


7-4 

Set Cursor Height 

0000 b Height = 1 pixel. 

0001 b Height = 2 pixels. 


: 

: 


0000 R/W 

3-0 

Note: In normal font, the cursor width fixed to one byte(8 pixels). And 

cursor’s height is from 1~16pixels that depends on Bit[7:4]. In vertical 

font, the cursor height fixed to 16 pixels, and width is from 1~8 pixels 

that depends on Bit[6:4]. 

Set Line Gap 

0000 b Gap = 1 pixel. 

0001 b Gap = 2 pixels. 


: 

: 


0000 R/W 


Version 1.3 



REG [12h] Memory Access Mode Register (MAMR) 


7 

Cursor Auto Shifting Direction 

0 : Cursor moves horizontally (left to right) first then vertically (top to 

down). 

1 : Cursor moves vertically first then horizontally. 

Note: In graphic mode, the cursor moving is treated as unit of bytes in 

horizontal direction. At vertical direction, it’s treated as unit of bit. At 

text mode, the bit is ignored, and the cursor moving is always in 

horizontal direction. 

Display Layer and Display Mode Selection 

0 0 0 : Gray Mode. In this mode, each pixel consists with 2 continuous 

bits in memory data. With the FRC methodology, 4-level-gray 

mode is implemented. The bit mapping is list as below. 

bit1 bit0 Gray 

--------------------------------------------------- 

0 0 Level1 (Lightest) 

0 1 Level2 

1 0 Level3 

1 1 Level4 (Darkest) 

0 R/W 

6-4 

3-2 

1-0 

Note: Gray mode doesn’t support text-mode input. 

0 0 1 : Show DDRAM1 data on screen. 

0 1 0 : Show DRRAM2 data on screen. 

0 1 1 : Show Two Layer Mode. The display rule depends on Bit-3 and 

Bit-2 as following. 

1 0 X : NA. 

1 1 0 : Extension Mode (1), the panel will show both DDRAM1 and 

DDRAM2 data on the screen. The RA8806 is available for 

640x240 pixels panel. 

1 1 1 : Extension Mode (2), the panel will show both DDRAM1 and 

DDRAM2 on the screen. The RA8806 is available for 320x480 

pixels panel. 

Two Layer Mode Selection 

Combine the data of DDRAM1 and DDRAM2 on the screen when 

Bit[6:4] is set as “011”. 

0 0 : DDRAM1 “OR” DDRAM2. 

0 1 : DDRAM1 “XOR” DDRAM2. 

1 0 : DDRAM1 “NOR” DDRAM2. 

1 1 : DDRAM1 “AND” DDRAM2. 

MPU Read/Write Layer Selection 

0 0 : Access CGRAM.(512Byte) 

0 1 : Access DDRAM1. 

1 0 : Access DDRAM2. 

1 1 : Access both DDRAM1 and DDRAM2 concurrently 

001 R/W 

00 R/W 

01 R/W 


Version 1.3 



REG [20h] Active Window Right Register (AWRR) 



Active Window Right Position Segment-Right 

5-0 

Note: AWRR must be equal or larger then AWLR, and less or equal 

then the value 27h (40 in decimal). 

Note: 

REG[20h, 30h, 40h, and 50h] are used to dominate an active window for line/row changing when writing 

data. Users can use these four registers to set the left/right/top/bottom boundary of active window. When 

data goes beyond the right boundary of it, the cursor will automatically change the next line to write data. It 

will move to the left boundary of new line in active window. When the data comes to the right-bottom corner, 

the next write will cause the cursor to move to the left-top corner. 

REG [21h] Display Window Width Register (DWWR) 



5-0 

Set Display Window Width Position Segment-Width 

Segment-Right = (Segment Number / 8) – 1 

If LCD panel resolution is 320x240, the value of the register is: 

( 320 / 8 ) - 1 = 39 = 27h 

Note: 

REG[21h, 31h] are used to set Display Window Resolution. Users can set the viewing scope of Display 

Data RAM. Column width (DWWR) of RA8806 can be set between 0h ~ 27h, and Row height (DWHR) can 

be set between 0h ~ EFh. 

27h 

27h 

R/W 

R/W 

REG [30h] Active Window Bottom Register (AWBR) 


7-0 

Active Window Bottom Position Common-Bottom 

Note: AWBR must be equal or larger then AWTR, and less or equal 

then the value EFh(239 in decimal) 

REG [31h] Display Window Height Register (DWHR) 


7-0 

Display Window Height Position Common- Height 

Common_ Height = LCD Common Number –1 

If LCD panel resolution is 320x240, the value of the register is: 

240 – 1 = 239 = EFh 

EFh 

EFh 

R/W 

R/W 


Version 1.3 



REG [40h] Active Window Left Register (AWLR) 



5-0 

Active Window Left Position Segment-Left 

Note: AWLR must be equal or less then AWRR, and less then the 

value 27h(39 in decimal) 

00h R/W 

REG [50h] Active Window Top Register (AWTR) 


7-0 

Active Window Top Position Common-Top 

Note: AWTR must be equal or less then AWBR, and less then the 

value EFh (239 in decimal) 

REG [60h] Cursor Position X Register (CURX) 



5-0 

Cursor Position of Segment / RAM0 Address[4:0] 

Define the cursor address of segment, a value from 0h ~ 27h(0 ~ 40 in 

decimal) 

When CGRAM write mode is selected (REG[12h] Bit[1:0] = 00b), the 

Bit[4:0] is the address for writing bit-map data. When create a full-size 

font, normally set to 0. When create an odd half-size font, normally set 

to 0, and set 10h for even font. 

REG [61h] Begin Segment Position Register of Scrolling (BGSG) 



5-0 

Segment Start Position of Scrolling Mode 

REG[61h] defines the start position (left boundary) of scroll window, it 

must be a value that less or equal to the REG[62h], which defines the 00h R/W 

end position(right boundary) of scroll window. Also it must be less 

then the value of 27h (40 in decimal), for the Display Data RAM limit. 

Note: 

REG[61h, 62h, 71h, 72h] dominate a named scroll window for scroll function. They must be set before the 

scroll function is enable. 

REG [62h] End Segment Position Register of Scrolling (EDSG) 



Segment End Position of Scrolling Mode 

REG[62h] defines the end position(right boundary) of scroll window, it 

5-0 must be a value that larger or equal to the REG[61h], which defines 

the end position(left boundary) of scroll window. Also it must be less 

or equal then the value of 27h(40 in decimal), for the Display Data RAM 

limit. 

00h R/W 

00h 

00h 

R/W 

R/W 


Version 1.3 



REG [70h] Cursor Position Y Register (CURY) 


7-0 

Cursor Position of Common / RAM0 Address[8:5] 

Define the cursor address of common, a value from 0h ~ EFh(0 ~ 239 

in decimal). 

When CGRAM write mode is selected (REG[12h] Bit[1:0] = 00b), the 

Bit[3:0] is indicate which font will be created. And Bit[7:4] are not 

available. 

00h 

R/W 

REG [71h] Scrolling Action Range Begin Common Register (BGCM) 


7-0 

Common Start Position of Scrolling Mode 

REG[71h] defines the begin position(top boundary) of scroll window, it 

must be a value that less or equal to the REG[72h], which defines the 

end position(bottom boundary) of scroll window. Also it must be less 

then the value of EFh (239 in decimal), for the Display Data RAM limit. 

00h R/W 

REG [72h] Scrolling Action Range END Common Register (EDCM) 


Common Ending Position of Scrolling Mode 

REG[72h] defines the end position(bottom boundary) of scroll window, 

7-0 

it must be a value that larger or equal to the REG[71h], which defines 

the end position(top boundary) of scroll window. Also it must be less 

or equal then the value of EFh (239 in decimal), for the Display Data 

RAM limit. 

00h R/W 

REG [80h] Blink Time Register (BTMR) 


Cursor Blink Time and Scroll Time 

Blinking Time = Bit[7:0] x (Frame width) 

7-0 

Frame width = 1/Frame Rate 

00h 

R/W 

The Frame Rate is depends on the DWWR and DWHR and ITCR 

setting. 

Notes: 

1. The Setting also determines the scroll moving speed. 

2. The Frame width is the time that the controller scan whole panel, it depends on the system clock 

frequency, setting of display window, driver interface (4-bits/8-bits), Idle time (ITCR), and dual mode or 

gray scale mode, etc. 


Version 1.3 



REG [90h] Idle Time Counter Register (ITCR) 


Idle Time Setting, in count of system clock. 

The value can determine the scan time of each COM of the LCD. 

In which, 

COM_PRD = ( COM_SCAN + ITCR) x XCK_PRD 

COM_SCAN = (SEG_NO/LD_WIDTH) x (1 + EXT_MD) 

XCK_PRD = 1 / XCK 

COM_PRD: The finally scan period for each COM(Unit : ns). 

7-0 

COM_SCAN: The really scan time for each COM. 

XCK_PRD: One cycle time of XCK. XCK is depends on the system 

clock(CLK) and REG[01h] Bit[3:2]. If system clock is 

8MHz, REG[01h] Bit[3:2] = 10b, then XCK_PRD = 250ns. 

00h 

R/W 

SEG_NO: Segment number, i.e. 240x160 panel, SEG_NO = 240. 

EXT_MD: In extension mode1 or 2(REG[12h] Bit[6:4] = 111b or 110b), 

the EXT_MD = 1, otherwise EXT_MD = 0. 

LD_WIDTH: Driver data width. If LCD driver data bus is 4-bits then 

LD_WIDTH = 4. If LCD driver data bus is 8-bits then 

LD_WIDTH = 8. Please refer pin “DW” description of 

Section 4-3. 

REG [A0h] Key-Scan Control Register 1 (KSCR1) 


7 

Key-Scan Enable Bit 

1 : Enable. 

0 R/W 

0 : Disable. 

6 

Key-Scan Matrix Selection 

1 : 4x8 Matrix(KOUT[3:0] is used, KOUT[7:4] please keep floating) 

0 R/W 

0 : 8x8 Matrix(KOUT[7:0] is used) 

5-4 

Key-Scan Data Sampling Times 

De-bounce times of scan frequency. 

0 0 : 4 

0 1 : 8 

00 R/W 

1 0 : 16 

1 1 : 32 

3 

LNGKEY_EN : Long Time Key Function Enable 

LNGKEY_EN = 0 Long key function is disable. 

LNGKEY_EN = 1 Long key function is enable. 

0 R/W 


Version 1.3 



2-0 

KF2-0: Key-Scan frequency. 

If system clock is 10MHz, then the related Key-Scan timing are as 

following: 

KF2 KF1 KF0 

Key-Scan 

Pulse Width 

(KOUT period) 

Key-Scan 

Cycle (4x8) 

Key-Scan 

Cycle (8x8) 

0 0 0 16µs 64µs 128µs 

0 0 1 32µs 128µs 256µs 

0 1 0 64µs 256µs 512µs 

0 1 1 128µs 512µs 1.024ms 

1 0 0 256µs 1.024ms 2.048ms 

1 0 1 512µs 2.048ms 4.096ms 

1 1 0 1.024ms 4.096ms 8.192ms 

1 1 1 2.048ms 8.192ms 16.384ms 

000 R/W 

REG [A1h] Key-Scan Controller Register 2(KSCR2) 


7 

Key-Scan Wakeup Function Enable Bit 

0: Key-Scan Wakeup function is disable. 

0 R/W 

1: KEY-SCAN Wakeup function is enable. 


3-2 

Long Key Timing Adjustment 

00 : About 0.625sec(for 8MHz Clock source) 

01 : About 1.25sec(for 8MHz Clock source) 

00 R/W 

10 : About 1.875 sec(for 8MHz Clock source) 

11 : About 2.5 sec(for 8MHz Clock source) 

1-0 

Numbers of Key Hit. 

00 : No key is pressed 

01 : One key is pressed, read REG[A2h] for the key number. 

10 : Two key is pressed, read REG[A2h ~ A3h] for the key number. 

11 : Three key is pressed, read REG[A2h ~ A4h] for the key number. 

00 R 

REG [A2h ~ A4h] Key-Scan Data Register (KSDR0 ~ 2) 


7-0 

Key Strobe Data 

The corresponding key number that is pressed. Please reference 

Section 6-5 "Key-Scan”. 

FFh R 

REG [B0h] Memory Write Command Register (MWCR) 


7-0 

Memory data write command from the cursor position. 

Note: Write memory data, user must write the MWCR command first, 

then write DATA cycle. 

NA R/W 


Version 1.3 



REG [B1h] Memory Read Command Register (MRCR) 


Memory data read command from the cursor position. 

7-0 Note: Memory read cycle in text mode, the cursor move in same 

behavior like graphic mode. B1h will perform a pre-read function. So 

the cursor position will increase after the MRCR command is write. 

NA R/W 

REG [C0h] Touch Panel Control Register 1 (TPCR1) 


7 

Touch Panel Enable Bit 

1 : Enable. 

0 R/W 

0 : Disable. 

TP Sample Time Adjusting 

000 : Wait 50µs for ADC data ready. 





6-4 101 : Wait 1.6ms for ADC data ready. 

110 : Wait 3.2ms for ADC data ready. 

000 R/W 

111 : Wait 6.4ms for ADC data ready. 

Note: When touch panel detects the Touch event, to avoid the signal 

instability, the sampled time is delayed to wait the signal stable. The 

TP Sample Time Adjusting and ADC Clock Convert Speed relation 

just refer to Section 6-4-3. 

Touch Panel Wake-up Enable: 

3 

1 : Touch panel can wake-up the Sleep mode(At the condition that 

ADC is enabled). 

0 R/W 

0 : Disable the touch panel wake-up function 

2-0 

ADC Clock Convert Speed 

0 0 0 : CLK / 4 

0 0 1 : CLK / 8 

0 1 0 : CLK /16 

0 1 1 : CLK / 32 

1 0 0 : CLK / 64 

1 0 1 : CLK / 128 

1 1 0 : CLK / 256 

1 1 1 : CLK / 512 

The “CLK” means system clock. 

000 R/W 

REG [C1h] Touch Panel X High Byte Data Register (TPXR) 


7-0 Touch Panel X Data Bit[9:2](Segment) 00h R 

REG [C2h] Touch Panel Y High Byte Data Register (TPYR) 


7-0 Touch Panel Y Data Bit[9:2] (Common) 00h R 


Version 1.3 



REG [C3h] Touch Panel Segment/Common Low Byte Data Register (TPZR) 



3-2 Touch Panel Y Data Bit[1:0] (Common) 00 R 

1-0 Touch Panel X Data Bit[1:0] (Segment) 00 R 

REG [C4h] Touch Panel Control Register 2 (TPCR2) 


7 

TP Manual Mode Enable 

1 : Using the manual mode. 

0 R/W 

0 : Auto mode. 

6-2 Reserved 00h R 

1-0 

Mode selection for TP Manual Mode 

00 : IDLE mode: ADC idles. 

01 : Wait for TP event, touch panel event could cause the interrupt or 

be read from REG[0Fh] B3. 

10 : Latch X data, in the phase, X Data can be latched in REG[C1h] 

and REG[C3h]. 

11 : Latch Y data, in the phase, Y Data can be latched in REG[C2h] 

and REG[C3h]. 

00 R/W 

REG [D0h] PWM Control Register (PCR) 


7 

PWM enable 

1 : Enable 

0 R/W 

0 : Disable, PWM_OUT level depends on the REG[D0h] Bit-6. 

6 

PWM Disable Level 

0 : PWM_OUT is Normal L when PWM disable or Sleep mode. 

0 R/W 

1 : PWM_OUT is Normal H when PWM disable or Sleep mode. 


3-0 

PWM Clock Source Divide Ratio 

0000 b CLK / 1 

0001 b CLK / 2 

0010 b CLK / 4 

0011 b CLK / 8 

: 

: 

1111 b CLK / 32768 

0000 R/W 

The “CLK” means system clock. For example, CLK is 8MHz: 

0000 b PWM clock source = 8MHz, 

0001 b PWM clock source = 4MHz, 

: 

: 

1111 b PWM clock source = 244Hz. 


Version 1.3 



REG [D1h] PWM Duty Cycle Register (PDCR) 


7-0 

PWM Cycle Duty Selection Bit 

00h 1 / 256 

01h 2 / 256 High period 

02h 3 / 256 High period 

: 

: 

FFh 256 / 256 High period 

REG [E0h] Pattern Data Register (PNTR) 


7-0 

Data Written to DDRAM(Display Data RAM) 

The pattern that will be filled to active window in memory clear 

function. 

When REG[F0h] Bit-3 is ‘1’, the data in the REG[E0h] will be filled to 

the whole active window. 

00h R/W 

00h 

R/W 

REG [F0h] Font Control Register (FNCR) 


7 

ISO8859 Mode 

0 : Disable. The contents of ASCII block 1 ~ 4 are show as Table C-1~ 

Table C-4 of Appendix B. 

0 R/W 

1 : Enable. The ASCII block 1 ~ 4 indicate the ISO8859-1 ~ 4 

standard and show as Table C-5 ~ Table C-8 of Appendix C. 


3 

Memory Clear Function 

Write Function 

0 : No Action. 

1 : Memory clear function active, fill the data of FNTR to Active 

window. 

0 R/W 

2 

1-0 

When this bit is set to “1”, RA8806 will automatically read PNTR data, 

and fill it to Active window (Range: [AWLR, AWTR] ~ [AWRR, 

AWBR]), after clear completed, this bit will be cleaned to “0”. 

ASCII Mode Enable 

1 : All input data will be decoded as ASCII (00h ~ FFh) 

0 : In text mode (REG[00h] Bit-3), the RA8806 will check the first 

written byte data first. If less then 80h then it’s treated as ASCII 

(Half-size). Or it’s treated as a full-size text(GB, BIG5 or Usercreated 

font). 

ASCII Blocks Select 

0 0 : Map to ASCII block 1. (Table C-1 and Table C-5 of Appendix C.) 




0 R/W 

00 R/W 


Version 1.3 



REG [F1h] Font Size Control Register (FVHT) 


7-6 

Set Character Horizontal Size 

0 0 : One Time of normal font width. 

0 1 : Two Times of normal font width. 

00 R/W 

1 0 : Three Times of normal font width. 

1 1 : Four Times of normal font width. 

5-4 

Set Character Vertical Size 

0 0 : One Time of normal font height. 

0 1 : Two Times of normal font height. 

00 R/W 

1 0 : Three Times of normal font height. 

1 1 : Four Times of normal font height. 



Version 1.3 



6. Function Description 

6-1 MPU Interface 

6-1-1 MPU Type 

The RA8806 support 8080 or 6800 compatible MPU interface. When the pin “MI” is pull low then the 

MPU interface is set to 8080 compatible. If “MI” pulls high then the MPU interface is defined as 6800 

compatible. And the pin “DB” is used to select the 8080 MPU data bus is 4-bits or 8-bits. When “DB” 

is pulled low, then the data bus for data transition is 4-bits. If pin “DB” pull high, the data transition is 

8-bits. The option of 4-bits or 8-bits data bus is for both 8080 and 6800 MPU. Of course, if used 4- 

bits interface then the 8080 MPU has to take double time to communicate with RA8806. In order to 

reduce the transmission line interference between MPU interface and RA8806, we suggest that a 

small capacitor to the GND should be added at the signal of ZCS1、ZRD、ZWR, please see the 

following Figure 6-1. 

8080 

MPU 


A0 

RS 

A1-A7 

IORQ 

Decoder 

ZCS1 

CS2 

MI 

D0-D3(D0 -D7) 

RD 

WR 

RES 

DATA0-3(DATA0-7) 

ZRD 

ZWR 

ZRST 

Figure 6-1 : 8080 (4/8-bits) MPU Interface 

6800 

MPU 


VDD 

A0 

RS 

A1-A7 

VMA 

Decoder 

ZCS1 

CS2 

MI 

D0-3(D0-D7) 

EN 

R/W 

RES 

DATA0-3(DATA0-7) 

EN 

ZRW 

ZRST 

Figure 6-2 : 6800 (4/8-bits) MPU Interface 


Version 1.3 



t AH8 

RS 

ZCS1 

CS2 

t AS8 

t CYC8 

ZWR 

ZRD 

t CC8 

t DS8 

t DH8 

DATA 

(Write) 

DATA 

(Read) 

t ACC8 

t OH8 

Figure 6-3 : 8080 MPU Interface Waveform 

Table 6-1 : 8080 MPU Interface Timing 

Symbol 

Description 

Min. 

Rating 

Max. 

Unit 

Condition 

t CYC8 Cycle time 2*tc -- ns 

tc = one system clock period 

t CC8 Strobe Pulse width 50 -- ns 

t AS8 Address setup time 0 -- ns 

t AH8 Address hold time 20 -- ns 

t DS8 Data setup time 30 -- ns 

t DH8 Data hold time 20 -- ns 

t ACC8 Data output access time 0 20 ns 

t OH8 Data output hold time 0 10 ns 


Version 1.3 



t AH6 

RS 

ZRW 

ZCS1 

CS2 

t AS6 

t CYC6 

EN 

t CC6 

DATA 

(Write) 

t DS6 

t DH6 

DATA 

(Read) 

t ACC6 

t OH6 

Figure 6-4 : 6800 MPU Interface Waveform 

Table 6-2 : 6800 MPU Interface Timing 

Symbol 

Description 

Min. 

Rating 

Max. 

Unit 

Condition 

t CYC6 Cycle time 2*tc -- ns 

t CC6 Strobe Pulse width 50 -- ns 

tc is one system clock period: 

tc = 1/CLK 

t AS6 Address setup time 0 -- ns 

t AH6 Address hold time 20 -- ns 

t DS6 Data setup time 30 -- ns 

t DH6 Data hold time 20 -- ns 

t ACC6 Data output access time 0 20 ns 

t OH6 Data output hold time 0 10 ns 


Version 1.3 



6-1-2 Command Write 

According to the Table 5-1, RA8806 accept 4 cycles through MPU interface. If users want to write 

command to RA8806, then a Command cycle has to execute first, and then execute a Data Write 

cycle. The “Command Write” means write function data to register. After these two cycles, the Data 

will write into the indicative Register. Please see the following Figure 6-5 (1). 

In Table 6-1 of Section 6-1-1, each command of RA8806 is take 2 cycles, and the minimum cycle 

time is 2*tc. So totally the minimum time of command write need 4*tc. See following Table 6-3. 

If the secondary cycle is a “Data Read”, then user could read the register content. See the following 

Figure 6-5 (2). Note the Figure 6-5 to Figure 6-7 are use the 8080 MPU interface as examples. 

RS 

ZCS1 

ZWR 

ZRD 

DATA[7:0] REG# DATA 

(1) Command Write (Write Data to Register) 

RS 

ZCS1 

ZWR 

ZRD 

DATA[7:0] REG# DATA 

(2) Read Data from Register 

Figure 6-5 : Command Write and Register Read Cycle 

Table 6-3 : Command Access Time Table 

System Clock Command Access Time 

4MHz 1µs 

6 MHz 667ns 

8 MHz 500ns 

10 MHz 400ns 

12 MHz 333ns 


Version 1.3 



6-1-3 Memory Write/Read 

When users want to write data to memory – DDRAM or CGRAM, then a special Command cycle 

has to execute first, the register have to assign to “B0h” on Data Bus. Then the following Data Write 

cycle will write data into memory. If users want to read data from memory, then the register has to 

assign to “B1h” on Data Bus in Command Write cycle. Please see the following Figure 6-6 (1) and 

(2). 

RS 

ZCS1 

ZWR 

ZRD 

DATA[7:0] B0h DATA1 DATA2 DATAn 

(1) Memory Write (Write Data to DDRAM) 

RS 

ZCS1 

ZWR 

ZRD 

DATA[7:0] 

B1h DATA1 DATA2 DATAn 

(2) Memory Read (Read Data from DDRAM) 

Figure 6-6 : Memory Write/Read Cycle 

6-1-4 Status Read 

RA8806 provides a dedicate Status Read cycle to help users know the status of RA8806. Please 

refer to following Figure 6-7 and the beginning of Section 5-2 “Register Description”. 

RS 

ZCS1 

ZWR 

ZRD 

DATA[7:0] 

Status DATA 

Status Register Read 

Figure 6-7 : Status Read Cycle 


Version 1.3 



6-2 Driver Interface 

The main function of Driver Interface is to generate Frame (Pin “FR”), Latch Pulse (Pin “LP”), “YD” and 

Data Bus (LD[7:0]) for external LCD driver IC. RA8806 could both support 4-bits and 8-bits LCD driver 

interface. Pin “DW” is for LCD driver data bus selection. If “DW” pulls high then 8-bits LCD driver is used. 

If pull low then 4-bits LCD driver is used. Figure 6-8 is the LCD interface of RA8806. 


LCD Driver 

YD 

FR 

LP 

FLM 

M 

LP 

Common Signals 

STN 

Dot Matrix 

LCD Panel 

ZDOFF 

/DISPOFF 

XCK 

LD[7:0] 

CP 

D[7:0] 

Segment Signals 

Figure 6-8 : The Interface of RA8806 and LCD Driver 

Figure 6-9 is the timing waveform of RA8806 and LCD Driver. Users could also refer to Section 4-4 

“LCD Driver Interface” for LCD driver pin description. 

For 320x240: Total 240 

LP for each Frame 

FR 

YD 

LP 

XCK 

1st line 

FR 

YD 

LP 

XCK 

LD 

(Data) 

Figure 6-9 : The Waveform of RA8806 and LCD Driver 


Version 1.3 



Figure 6-10 is the application diagram of RA8806. In this example, we use 80-channels LCD Drivers to 

process Common and Segment activity of 320x240 LCD Panel. RA8806 send FR, LP, YD, Data 

Bus(LD[3:0] and clock(XCK) signals to Segment/Common drivers. The Figure 6-11 is the example for 

160x160 panel application. 

Figure 6-10 : Application Circuit Diagram for 320x240 Panel 


Version 1.3 



EIO1 

160-channel 

(Common) 

Y1~Y160 

VDD 

VSS 

MD 

S/C 

L/R 

DI0~DI7 

FR 

LP 

DISPOFF 

XCK 

160*160 Dot 

LCD Panel 

EIO2 


YD 

Y1~Y160 

FR 

LP 

ZDOFF 

XCK 

LD[7:0] 

XCK 

EIO2 

DISPOFF 

DI0~DI7 

LP 

L/R 

FR 

160-channel 

(Segment) 

S/C 

MD 

EIO1 

Figure 6-11 : Application Circuit Diagram for 160x160 Panel 

Table 6-4 is the RA8806 driver signals mapping to different driver ICs’ pin names. Note, do not need 

add any capacitor on these for LCD driver signals. If add external capacitor on these pins to 

ground or VDD, then the maximum limitation is 30pF. 

Table 6-4 : Driver IC I/F Name vs. RA8806 


Driver I/F 

Driver IC I/F Name 

Definition of Driver IC I/F 

LP 

LP 

Data Latch Clock 

Latch Pulse in one line 

LOAD Latch pulse of display data 

CL1 

Data Latch Pulse 

CP 

Data Shift Clock 

Clock pulse for segment shift register 

XCK 

SCP 

Shift Clock Pulse for X-Drivers 

CL2 

Data Shift Pulse 

HSCP Shift Clock Pulse 

FLM 

Scan Start-up Signal 

First Line Marker 

FR 

Frame Pulse 

YD 

Frame start signal(First line mark of common 

FRAME 

signal) 

CDATA Synchronous Data 

FR 

DF(M) 

Switch signal to convert LCD drive waveform 

into AC 

LD[7:0] D[7:0] LCD Data Bus 

/DISPOFF Display OFF 

ZDOFF 

/D.OFF Display OFF 

DISP 

Display OFF 


Version 1.3 



6-2-1 Display Resolution 

RA8806 support many different resolution of LCD panel. For different resolution of panel, RA8806 

could change the setting of some registers like DWWR and DWHR to modify display window size. 

And use registers AWRR, AWBR, AWLR and AWTR to change the active window size. 

For example, if 320x240 LCD panel is used, then the related register setting is as following: 

DWWR = (320 / 8) - 1 = 39 = 27h 

DWHR = 240 – 1 = 239 = EFh 

The active window range is less than display window. So user has to care the rule as following: 

1. DWWR ≥ AWRR ≥ AWLR 

2. DWHR ≥ AWBR ≥ AWTR 

RA8806 supports a variety of LCD modules, the setting of register depnding on different resolution 

of LCD module is list at below table. 

Table 6-5 : Registers Setting for LCM Resolution 

Panel 

Resolution 

Segment 

Common 

REG[21h] 

DWWR 

REG[31h] 

DWHR 

160*80 160 80 13h 4Fh 

160*128 160 128 13h 7Fh 

160*160 160 160 13h 9Fh 

240*64 240 64 1Dh 3Fh 

240*128 240 128 1Dh 7Fh 

240*160 240 160 1Dh 9Fh 

320*240 320 240 27h EFh 

6-2-2 Display Window and Active Window 

The RA8806 provides two windows for real application -- Display Window and Active Window. The 

Display Window is the actual resolution of LCD panel. Active is a sub-window in Display Window. 

The boundary of cursor shift depends on the active window. The relative registers of the two 

windows are as the following table. 

Table 6-6 

Reg. Bit_Num Description Reference 

AWLR Bit [5:0] Define left boundary of the active window REG[40h] 

AWRR Bit [5:0] Define right boundary of the active window REG[20h] 

AWTR Bit [7:0] Define top boundary of the active window REG[50h] 

AWBR Bit [7:0] 

Define bottom boundary of the active 

REG[30h] 

window 

DWWR Bit [5:0] Define the width of the display window REG[21h] 

DWHR Bit [5:0] Define the height of the display window REG[31h] 


Version 1.3 



For RA8806, if LCD panel resolution is 320x240 pixels then the display window resolution is 

320x240. We can create an active window in the display window like Figure 6-12. This figure show 

the display resolution is 320x240, and a 160x160 active window is on the upper-middle. The relative 

setting of the active window as following: 

LCD_CmdWrite ( 0x40 ); // AWLR = 09h = 9 ( 80 / 8) – 1 

LCD_DataWrite ( 0x09 ); 

LCD_CmdWrite ( 0x20 ); // AWRR = 1Dh = 29 ( 240 / 8 ) – 1 

LCD_DataWrite ( 0x1D ); 

LCD_CmdWrite ( 0x50 ); // AWTR = 00h = 0 


LCD_CmdWrite ( 0x30 ); // AWBR = 9Fh = 159 160 – 1 

LCD_DataWrite ( 0x9F ); 

LCD_CmdWrite ( 0x21 ); // DWWR = 27h = 39 ( 320 / 8 ) – 1 


LCD_CmdWrite ( 0x31 ); // DWHR = EFh = 239 240 – 1 

LCD_DataWrite ( 0xEF ); 

320 

0 1 2 …….... 79 80 ………………………… 239 240 ……… 319 

0 

1 

2 

: 

: 

: 

: 

: 

: 

: 

159 

160 

: 

: 

: 

239 

Active Window 

80 80 

160 x 160 

80 

Display Window 

320 x 240 

240 

Figure 6-12 : RA8806 Display Window and Active Window 


Version 1.3 



For RA8806, if LCD resolution is 240x160 pixels then the display window resolution is 240x160. We 

can create an active window in the display window like Figure 6-13. This figure show the display 

resolution is 240x160, and a 120x120 active window is on the upper-left. The relative setting of the 

active window as following: 

LCD_CmdWrite ( 0x40 ); // AWLR = 00h = 0 


LCD_CmdWrite ( 0x20 ); // AWRR = 0Eh = 14 ( 120 / 8 ) – 1 

LCD_DataWrite ( 0x0E ); 

LCD_CmdWrite ( 0x50 ); // AWTR = 00h = 0 


LCD_CmdWrite ( 0x30 ); // AWBR = 77h = 119 120 – 1 


LCD_CmdWrite ( 0x21 ); // DWWR = 1Dh = 29 ( 240 / 8 ) – 1 

LCD_DataWrite ( 0x1D ); 

LCD_CmdWrite ( 0x31 ); // DWHR = 9Fh = 159 160 – 1 

LCD_DataWrite ( 0x9F ); 

240 

0 

1 

2 

: 

: 

: 

: 

: 

: 

: 

119 

120 

: 

: 

: 

159 

0 1 2 ………………………. 119 120 ……………………… 239 

Active Window 

120 x 120 

Display Window 

240 x 160 

160 

Figure 6-13 : Display Window and Active Window 


Version 1.3 



6-2-3 Com/Seg Scan Direction 

RA8806 supports a special feature to reverse the Common and Segment signal. User could use 

this feature to change the direction of cursor and display data. If use text rotate function and set 

CDIR = 1, then use could show text in vertical display. Please refer to Section 6-10-4. 

Table 6-7 


MISC 

Bit 1 

Bit 0 

Define the order of Segment signals. (SDIR) 

Define the order of Common signals. (CDIR) 

REG[01h] 

SEG0 .............................................. SEG319 

COM0 

: Cursor Moving way 

: 

: 

: 

: 

: 

: 

: 

COM239 

(1) SDIR = 0 

SEG0 …………………………………. SEG319 

COM0 

: 

Cursor Moving way 

: 

: 

: 

: 

: 

: 

: 

COM239 

(2) SDIR = 1 

Figure 6-14 : Example for Change Segment Direction 

6-2-4 Idle Time Counter (ITCR) 

ITCR(REG[90h]) is used to determine the idle time during the LP peer-to-peer time. It has following 

meanings in function. 

1. Adjusting the Frame Rate.(By extending the scan time of each COM) 

2. Avoiding the generation of “Flicker”. 

The “Flicker” is generated by the violation of LCD scan cycle and Memory write cycle. “Flicker” 

means the noise of the scan data at such violation. By setting the ITCR, user can write the display 

memory only at “Idle” time to eliminate the “Flicker”. 

XCLK 

LP 

ITCR 

COM_SCAN 

T_COM 

Figure 6-15 : Idle Time Period 

RA8806 scan time of each COM line can be calculated by the formulas. 


Version 1.3 



COM_PRD = ((SEG_NO/LD_WIDTH) x (1 + EXT_MD)) + ITCR ) x XCK_PRD 

In which the EXT_MD means extension mode is set or not, if REG[12h] Bit[6:4] = 110b/111b, 

EXT_MD = 1, or EXT_MD = 0. The “XCK_PRD” is one clock period of XCK. The XCK frequency is 

base on the system clock. It depends on the setting of Bit[3:2] of REG[MISC]. As to the Frame time 

and frame rate calculation. It would be: 

FRM_PRD = COM_PRD x COM# 

And 

FRM_Rate = 1 / FRM_PRD 

For example, when panel size is set to 320x240, system clock frequency is 8MHz, REG[MISC] 

Bit[3:2] = 10b, LCD driver data bus width is 4-bits, what the frame rate would be? 

The System Clock(CLK) is 8MHz, and REG[MISC] Bit[3:2] = 10b XCK = CLK/2, so the XCK_PRD 

is 250ns. 

XCK_PRD = 1 / (CLK/2) = 1/4MHz = 250ns 

COM_PRD = ( 320 / 4 + ITCR) x XCK_PRD = (80+ ITCR) x 250(ns) 

If the ITCR = A0h(160 in decimal): 

COM_PRD = (80+160) x 250ns = 240 x 250ns = 60µs 

The COM number is 240, so the frame period is: 

FRM_PRD = 60µs x 240 = 14.4 ms 

And the frame rate is: 

Frame Rate = 1 / 14.4 ms = 69.4 Hz 

We can see the effect that the ITCR setting to the corresponding frame rate. So we can use it to 

adjust the frame rate. Please refer to Appendix B - the Table B-1 ~ Table B-3. In those tables, we 

show some Frame Rate setting for difference resolution, system clock. But note the display quality is 

also depends on the module design and the material of liquid crystal. 

Table 6-8 


ITCR Bit [7:0] 

Define the idle time during the LP peer-topeer 

time. 

REG[90h] 

MISC Bit [3:2] Select the clock frequency of XCK. REG[01h] 


Version 1.3 



6-3 Display Data RAM (DDRAM) 

The RA8806 embedded two 9.6Kbyte Display Data RAMs – DDRAM1 and DDRAM2. It can use for two 

layers mono-display or one layer 4-gray-levels display. The maximum resolution of supporting LCD 

panel is 320Column x 240Row. There are two modes to write the DDRAM, text mode and graphics 

mode. It provides a flexible and easy way to make the display. 

6-3-1 Display Layer and Display Mode Selection 

There are 4 possible displays way at 2 Modes combination. 

1. Only show DDRAM1 or DDRAM2: One DDRAM data will show on the screen, and another one 

DDRAM can be standby or as a CGRAM to created special font or symbol by users. Please refer 

to Section 6-11 “User Defined Font” for detail description. 

2. Two Layer Mode: In this mode, the screen will show the combination data of DDRAM1 and 

DDRAM2. There are 4 types combination that set by REG[12H] Bit[3:2]. 

DDRAM1 “OR” DDRAM2 

DDRAM1 “XOR” DDRAM2 

DDRAM1 “NOR” DDRAM2 

DDRAM1 “AND” DDRAM2 

For detail please refer to Section 6-10-1-5 “Two Layer Display”. 

3. 4-Gray-level Mode: In gray mode, each pixel consists with 2 continuous bits in both DDRAM. 

4. Extension Mode: Two extension modes is support, and both DDRAM1 and DDRAM2 data will 

show on the screen. 

Horizontal extension mode (Max. resolution is 640 x 240 pixels). 

Vertical extension mode (Max. resolution is 320 x 480 pixels). 

6-3-2 Access Memory Selection 

There are one 512Byte CGRAM and two 9.6KByte DDRAMs in RA8806. The 512Byte CGRAM is 

used to generate user-define font, and the two DDRAM are used to store the display data. One of 

both DDRAM can be also store special font or symbol, that when only one DDRAM is active on the 

screen. Which RAM is available for MPU access is depending on the REG[12h] Bit[1:0]. Please 

refer to Section 5-2 “Register Description”. 

Table 6-9 


Bit [6:4] 

Display Layer and Display Mode Selection 

MAMR 

Bit [3:2] 


MPU Read/Write Memory Selection 

REG[12h] 

Bit [1:0] 


Version 1.3 



6-4 Touch Panel 

RA8806 built in a 10-bit ADC and control circuits to connect with 4-wires resistance type touch panel. 

Resistive Touch Panel is composed of two layer extremely thin resistive panel, such as Figure 6-16. 

There is a small gap between these two-layer panels. When external force press a certain point, the 

two-layer resistive panels will be touched, which is short. Because the end points of two-layer have 

electrodes (XL, XR, YU, YD), such as Figure 6-17, a comparative location will be detected with some 

switches in coordination. 

YU 

Y Plate 

X Plate 

Electrode 

XL 

YD 

XR 

Figure 6-16:Touch Panel 

VDD 

SW2 

YU 

Resistor -Y 

VDD 

SW0 

XL 

XR 

SW1 

Resistor -X 

YD 

SW3 

GND 

Figure 6-17 : Control Switch of Touch Panel 

Users only need to connect the touch panel signals -- XL, XR, YU, and YD to RA8806. It will 

continuously monitor the panel and wait for touch event. When the event is occurred, a divided voltage 

on panel caused by touch is sensed and transferred by ADC to determine the location. After the value of 

X-axis and Y-axis are transferred and stored in corresponding registers respectively, the touch panel 

controller will issue an interrupt to inform MPU to process it. 


Version 1.3 




VDD 

39Kohm 

Touch Panel 

X1 

XL 

X2 

XR 

Y1 

YU 

Y2 

YD 

0.01μF x 4 

Figure 6-18 : RA8806 Touch Panel Circuit 

RA8806 provides 2 modes (Auto and Manual) for touch panel application. 

Table 6-10 

Operation 

mode 

Auto 

Manual 

Event 

detection 

Interrupt 

Interrupt 

Polling 

Description 

When touch event happens, Read the corresponding X, Y 

coordination. 

When touch event happens, Read the corresponding X, Y 

coordination. 

Polling the touch event, and read the corresponding X, Y 

coordination. 


Version 1.3 



6-4-1 Auto Mode 

Auto mode is the easiest way to implement touch panel application. Please refer to the flow chart 

below. 

(1) Flowchart: 

Start 

Enable Touch Panel 

( REG[C0h] B7 = 1 ) 

ISR 

Set Auto Mode 

( REG[C4h] B7 = 0 ) 

Check INT Status 

( REG[0Fh] B0 = ? ) 

0 

Enable TP INT Mask 

( REG[0Fh] B4 = 1 ) 

Ext. INT Event 

1 

Read X, Y-axis 

( Read REG[C1h], 

REG[C2h], REG[C3h] ) 

Other Functions 

Execute Function 

Clear TP INT Status 

( REG[0Fh] B0 = 0 ) 

ISR Termination 

Figure 6-19 : Auto Mode Flowchart for Touch Screen 

Table 6-11 lists the used registers. 

Table 6-11 


TPCR1 Bit 7 EnableTouch Panel function REG[C0h] 

TPCR2 Bit 7 “Auto-Mode” or “Manual Mode” selection bit REG[C4h] 

INTR 

Bit 4 

Bit 0 

Touch Panel Hardware Interrupt enable bit 

Touch event status bit 

REG[0Fh] 

TPXR Bit [7:0] Touch Panel SEG data MSB byte REG[C1h] 

TPYR Bit [7:0] Touch Panel COM data MSB byte REG[C2h] 

TPZR 

Bit [3:2] 

Bit [1:0] 

Touch panel COM data LSB 2bit 

Touch panel SEG data LSB 2bit 

REG[C3h] 


Version 1.3 



(2) Program Example: 

Unsigned char X1,X2,Y1,Y2; 

Touch_Panel_Enable ( ); // Set TPCR1 Bit 7 to 1 

TP_Auto_Enable ( ); // Set TPCR2 Bit 7 to 0 

TP_INT_Mask_Enable ( ); // Set INTR Bit-4 to 1 

: 

: 

Execute other function 

// Jump to ISR when interrupt 

: 

: 

Int EXT_INT_Service_Routine 

{ 

LCD_CmdWrite ( INTR ); 

INT_Sta = LCD_DataRead ( ); 

// ISR entry 

// Check INT status 

If ( INT_Sta & 0x01 ) 

// Check If TP interrupt 

{ 

LCD_CmdWrite(TPXR); 

X1 = LCD_DataRead( ); // MSB of X 

LCD_CmdWrite(TPYR); 

Y1 = LCD_DataRead( ); // MSB of Y 

LCD_CmdWrite(TPZR); 

X2 = LCD_DataRead( ) & 0x03; // LSB two Bits of X 


Y2 = LCD_DataRead( ) & 0x0C; // Least two Bits of Y 

: 

: 

Execute corresponding function 

: 

: 

LCD_CmdWrite ( INTR ); // Clear Touch Panel status 

temp = LCD_DataRead ( ) & 0xfe; 


LCD_DataWrite ( temp ); 

} 

Else if (INT_Sta & 0x02) 

// Check if Key-Scan interrupt 

{ 

: 

: 

} 


// Check if Wakeup interrupt 

{ 

: 

: 

} 

} 


Version 1.3 



6-4-2 Manual Mode 

The “ Manual Mode” means that the operation process from “Touch event checking function” to 

“input Latch X data Y data”, the whole operation and setting process ( includes TPCR2[1:0]) and 

receiving data from XY coordinates are manual operated by programmer. The advantage of using 

Manual Mode is it allows programmer more flexible applications. In the condition that is over the 

range of RA8806 register setting, the user can still use the software method to control the TP 

function in a correct way. 

Touch Event can be detected from “Interrupt Mode” or “Polling Mode” that depend on the system 

configuration. The difference between the “Interrupt Mode” and “Polling Mode” are explained as 

following. 

6-4-2-1 External Interrupt Mode 

Under the “Interrupt Mode” the touch event detecting way is almost the same as “ Auto Mode”. The 

major processes are list as follows: 

1. Enable Touch Panel function. 

2. Change mode to “Manual mode”. 

3. Set the switch to 「Wait for touch event 」, Set TPCR2[1:0] to 01b. 

4. When interrupt asserts, check if TP interrupt. 

5. If yes, change the switch to 「Latch X data」, Set TPCR2[1:0] to 10b, wait for enough time 

to make the latch data stable and latched to TPXR and TPZR. 

6. Change the switch to「Latch Y data」, Set TPCR2[1:0] to 11b, wait for enough time to 

make the latch data stable and latched to TPYR and TPZR. 

7. Read X, Y data from TPXR, TPYR and TPZR, and clear the interrupt status. 

The registers for Interrupt Mode are explained as below: 

Table 6-12 


TPCR1 Bit 7 Enable Touch Panel function REG[C0h] 

TPCR2 

Bit 7 

Bit [1:0] 

TP Manual mode enable 

Mode selection for TP manual mode 

REG[C4h] 

INTR 

Bit 4 

Bit 0 

Touch Panel Interrupt Mask 

Touch Panel Detect Status bit 

REG[0Fh] 

TPXR Bit [7:0] Touch Panel X Data Bit[9:2](Segment) REG[C1h] 

TPYR Bit [7:0] Touch Panel Y Data Bit[9:2](Common) REG[C2h] 

TPZR 

Bit [3:2] 

Bit [1:0] 

Touch Panel Y Data Bit[1:0] (Common) 

Touch Panel X Data Bit[1:0] (Segment) 

REG[C3h] 


Version 1.3 



Please refer to the following flow chart and the setting examples for applying Interrupt Mode: 


Start 


( REG[C0h] B7 = 1 ) 

Set Manual Mode 

( REG[C4h] B7 = 1 ) 

Enable TP INT Mask 

( REG[0Fh] B4 = 1 ) 

ISR 

Check INT Status 

( REG[0Fh] B0 = ? ) 

1 

Latch X Data 

( REG[C4h][1:0] = 10 ) 

0 

Wait for TP event Mode 

( REG[C4h][1:0] = 01 ) 

Ext. INT Event 

Latch Y Data 

( REG[C4h][1:0] = 11 ) 




Other Functions 



( REG[0Fh] B0 = 0 ) 

ISR Termination 

Figure 6-20 : Manual Mode Flowchart for Touch Screen 


Version 1.3 




Unsigned char X1,X2,Y1,Y2; 

Touch_Panel_Enable ( ); // Set TPCR1 Bit-7 to 1 

TP_Manual_Enable ( ); // Set TPCR2 Bit 7 to 1 

TP_INT_Mask_Enable ( ); // Set INTR Bit-4 to 1 

Switch_Wait_TP_Event( ); 

// Set TPCR2[1:0] to 01b 

: 

: 


// Jump to ISR when interrupt 

: 

: 

Int EXT_INT_Service_Routine 

// ISR entry 

{ 




If ( INT_Sta & 0x01) 

// Check If TP interrupt 

{ 

Switch_Latch_X_data( ); // Set TPCR2[1:0] to 10b 

Delay_Time( ); 

// Delay enough time for X data stable 

Switch_Latch_Y_data( ); // Set TPCR2[1:0] to 11b 


// Delay enough time for Y data stable 


X1 = LCD_DataRead( ); // MSB of X 


Y1 = LCD_DataRead( ); // MSB of Y 


X2 = LCD_DataRead( ) & 0x03; // LSB two Bits of X 


Y2 = LCD_DataRead( ) & 0x0C; // LSB two Bits of Y 

: 

: 


: 

: 

LCD_CmdWrite ( INTR ); // Clear Touch Panel status 




} 



{ 

: 

: 

} 



{ 

: 

: 

} 

} 


Version 1.3 



6-4-2-2 Polling Mode 

Under the ”Polling Mode”, users need to decide and set the de-bounce time after the touch event, as 

well as the sampling time after latch by considering the real situation, thus more flexibilities for users 

apply this mode. 

The development procedures are explained as follows: 

1. Enable Touch Panel function 

2. Change mode to “Manual mode” 

3. Set the switch to「Wait for Touch event」, i.e., set TPCR2[1:0] to 01b. 

4. Read Touch Panel Event status from status register, check if the “Touch event” happens. 

5. When touch event happens, confirm the stability of it and set the switch to 「Latch X data」, 

i.e., TPCR2[1:0] set to 10b, wait for enough time to make the latch data stable and latched 

to TPXR and TPZR 

6. Set the switch to「Latch Y data」, i.e., TPCR2[1:0] set to 11b, wait for enough time to make 

the latch data stable and latched to TPYR and TPZR 

7. Read X, Y data from TPXR, TPYR and TPZR, and clear the interrupt status 

The settings for manual interrupt mode are described in the following table: 

Table 6-13 


TPCR1 Bit 7 Enable Touch Panel function 

Select operation mode to Auto-mode or 

Bit 7 

TPCR2 

Manual-mode. 

Bit [1:0] The switch of ADC controller for manual mode 

Touch panel event(Only activate in TP Manual 

Bit 3 

INTR 

mode) 

Bit 0 Touch Panel Detect Status bit 

TPXR Bit [7:0] Touch Panel X Data Bit[9:2](Segment) 

TPYR Bit [7:0] Touch Panel Y Data Bit[9:2] (Common) 

Bit [3:2] Touch Panel Y Data Bit[1:0] (Common) 

TPZR 

Bit [1:0] Touch Panel X Data Bit[1:0] (Segment) 

REG[C0h] 

REG[C4h] 

REG[0Fh] 

REG[C1h] 

REG[C2h] 

REG[C3h] 

Programmer can check the status of Touch Panel Event from the Bit-3 or Bit-0 of INTR, the 

difference between those two bits is : 

1. The Bit-3 of INTR reflects the current Touch status. When Touch event occurs, the Bit-3 is 1. 

When there is no Touch event, Bit-3 will be 0 and read only. 

2. The Bit-0 of INTR records the Touch status. When a Touch event occurs, the Bit-3 will be 1 

and however it won’t be clear automatically, it has to clear by programmer. 

It needs to be noted is that the REG[0Fh] Bit-3 is the direct output from ADC circuit, when touch 

panel is touched, the bit will respond with the event. When touch event is not stable, it needs to be 

de-bounced to check if it’s legal. The bit is only active at “Manual mode”. When setting RA8806 to 

“Auto-mode, the touch event will be automatically checked if it’s legal or not. Only the legal touch 

event will cause the interrupt. 


Version 1.3 



Please refer to the flowchart and setting examples for applying above methods: 


Start 


( REG[C0h] B7 = 1 ) 

Set Auto Mode 

( REG[C4h] B7 = 1 ) 

Wait for TP event Mode 

( REG[C4h][1:0] = 01 ) 

Latch X Data 

( REG[C4h][1:0] = 10 ) 

Delay enough time 

Latch Y Data 

( REG[C4h][1:0] = 11 ) 

Delay enough time 

0 Check TP Event 

( REG[0Fh] B3 = ? ) 

1 




Check TP Event 

100 times ? 

invalid 

Other Function 

valid 



( REG[0Fh] B0 = 0 ) 

Figure 6-21 : Polling Mode Flowchart for Touch Screen 


Version 1.3 




Touch_Panel_Enable ( ); // Set REG[C0h]. Bit-7 = 1 

TP_Manual_Enable ( ); // Set REG[C4h]. Bit-7 = 1 

Switch_Wait_TP_Event( ); // Set REG[C4h][1:0] = 01 

Touch_Sta_Valid = 0; 



// Initial Touch state 


// Check INTR.Bit-3 

{ 

for ( count = 0 ; count < 100 ; count++ ) // Check 100 times 

{ 


INT_Sta = LCD_DataRead( ); 

if (INT_Sta == 0) 

// When no touch 

{ 


// Touch is invalid 

break; 

} 

if ( count == 99 ) 

// When count 100 times, touch is valid 


} 

if (Touch_Sta_Valid ) 

{ 

Switch_Latch_X_data( ); // Set REG[C4h][1:0] = 10 


// Delay enough time 

Switch_Latch_Y_data( ); // Set REG[C4h][1:0] = 11 


// Delay enough time 


X1 = LCD_DataRead( ); // Read high byte of X-axis 


Y1 = LCD_DataRead( ); // Read high byte of Y-axis 


X2 = LCD_DataRead( ) & 0x03; // Read Least two Bits of X-axis 


Y2 = LCD_DataRead( ) & 0x0C; // Read Least two Bits of Y-axis 

: 


: 

LCD_CmdWrite ( INTR ); // Clear REG[0Fh]. Bit-0 




} 

} 

: 


: 

: 


Version 1.3 



6-4-3 Touch Panel Sampling Time Reference Table 

When using the auto mode of touch panel function, It is suggested to select suitable TP Sampling 

wait time while the ADC Clock Convert speed change, in order to avoid the TP Sample wait time 

error. Please refer to the following table for the ADC Sampling wait time REG[C0h][6:4]。 

Figure 6-21-A : Touch Panel Sampling Time Reference Table 

ADC Sampling Wait Time - REG[C0h] Bit[6:4] 

REG[C0h] [2:0] 

SYSTEM_CLK 

4M 6M 8M 10M 12M 

000 000 000 000 000 000 

001 000 000 000 000 000 

010 000 000 000 000 000 

011 001 001 000 000 000 

100 010 010 001 001 001 

101 011 011 010 010 010 

110 100 100 011 011 011 

111 101 101 100 100 100 


Version 1.3 



6-5 Key-Scan 

RA8806 features with Key-Scan circuit, and could be used as Keyboard function. It will help to integrate 

the system circuit that includes keyboard application. The below Figure 6-22 shows the basic application 

circuit of 8x8 Key-Pad. RA8806 already built-in pull-up resistors in the pins “KIN[7:0]”. 


KIN0 

KIN1 

KIN2 

KIN3 

KIN4 

KIN5 

KIN6 

KIN7 

KOUT0 

KOUT1 

KOUT2 

KOUT3 

KOUT4 

KOUT5 

KOUT6 

KOUT7 

Figure 6-22 : 8x8 Key-Pad Application 

The related Registers of Key-san function are KSCR, KSDR, and KSER. The RA8806 Key-Scan 

controller features are given below: 

1. Support with 4x8 or 8x8 Key-Scan Matrix 

2. Programmable setting of sampling times and scan frequency of Key-Scan 

3. Adjustable long key-press Timing 

4. Multi-Key is available ( maximum three keys at the same time) 

5. Allows the function of “ Key press to wake-up the system” 

Table 6-14 is the key code of mapping to key-pad matrix for normal press. The key code will be stored in 

REG[A2h] when key was pressed. If it was a long time press, then the key code is show as Table 6-15. 

Table 6-14 : Key Number Mapping Table (Normal Key) 

ROW # 

0 1 2 3 4 5 6 7 

0 

00h 

01h 

02h 

03h 

04h 

05h 

06h 

07h 

1 

10h 

11h 

12h 

13h 

14h 

15h 

16h 

17h 

2 

20h 

21h 

22h 

23h 

24h 

25h 

26h 

27h 

COL # 

3 

4 

30h 

40h 

31h 

41h 

32h 

42h 

33h 

43h 

34h 

44h 

35h 

45h 

36h 

46h 

37h 

47h 

5 

50h 

51h 

52h 

53h 

54h 

55h 

56h 

57h 

6 

60h 

61h 

62h 

63h 

64h 

65h 

66h 

67h 

7 

70h 

71h 

72h 

73h 

74h 

75h 

76h 

77h 


Version 1.3 



Table 6-15 : Key Number Mapping Table (Long Key) 

ROW # 

0 1 2 3 4 5 6 7 

0 

80h 

81h 

82h 

83h 

84h 

85h 

86h 

87h 

1 

90h 

91h 

92h 

93h 

94h 

95h 

96h 

97h 

2 

A0h 

A1h 

A2h 

A3h 

A4h 

A5h 

A6h 

A7h 

COL # 

3 

4 

5 

B0h B1h B2h B3h B4h B5h B6h B7h 

C0h C1h C2h C3h C4h C5h C6h C7h 

D0h D1h D2h D3h D4h D5h D6h D7h 

6 

E0h 

E1h 

E2h 

E3h 

E4h 

E5h 

E6h 

E7h 

7 

F0h 

F1h 

F2h 

F3h 

F4h 

F5h 

F6h 

F7h 

When the Multi-Key function is applied, the pressed keys will be saved in the system each with KSDR0, 

KSDR1 and KSDR2. Note that the priority of keys saving is determined on the value size of Key-code, 

not the orders of keys pressing, please refer to the following example: 

Press the Key-code in turn of 0x44, 0x00 and 0x22, press Multi-Key at the same time, the Key-code will 

be saved in KSDR: 

KSDR0 = 0x00 

KSDR1 = 0x22 

KSDR2 = 0x44 

The definition of Key-code is described in the registers KSDR0 ~ 2 [A2h ~ A4h]. The basic features of 

above Key-Scan settings are introduced as follows: 

Table 6-16 


Bit 7 

Key-Scan enable bit 

Bit 6 

Key-Scan size selection 

KSCR1 

Bit [5:4] 

Key-Scan sampling times setting 

REG[A0h] 

Bit 3 

Long key function enable 

Bit [2:0] 

Key-Scan scan frequency setting 

KSCR2 

Bit [3:2] 

Bit [1:0] 

long key timing adjustment 

Pressed key number 

REG[A1h] 

KSDR0 

KSDR1 

KSDR2 

Bit [7:0] Key code for pressed key REG[A2h ~ A4h] 

INTR 

Bit 5 

Bit 1 

Key-Scan interrupt enable 

Key-Scan Interrupt Status bit 

REG[0Fh] 


Version 1.3 



Besides, in the Sleep Mode, RA8806 allows the “Wake-up on Keystroke” function, if any key is pressed, 

the System Clock starts to oscillate, and de-bounce to check if the wake-up event is legal. If legal then 

after two Frame time, the Display on the panel will be lighted, then system will recover from the Sleep 

Mode. If not legal, the system clock is off again and keeps on the Sleep mode. Please refer to the 

description of “Power Mode” for the detail introduction of “Sleep Mode”. The settings for Wake-up 

function are explained as follows: 

Table 6-17 


KSCR2 Bit 7 

Bit 6 

INTR 

Bit 2 

Enable Key-Scan wake-up function 

Wake-up interrupt enable bit 

Wake-up Interrupt Status bit 

REG[A1h] 

REG[0Fh] 

Enabling the Key-Scan functions, programmer cans uses following methods to check keystroke. 

1) Software check method: to know the key be pressed from keeping check the status of Key-Scan 

(Bit-1 of INTR) 

2) Hardware check method: to know the key be pressed from external interrupt signal 

Please be aware that the status of Key-Scan (Bit-1 of INTR) has been set to “1” no matter which method 

is used, programmer have to clear the status to 0 after reading the correct Key Code, otherwise the 

interrupt will be kept that no more interrupt is visible again. 


Version 1.3 



The flowchart and sample settings for above applications are shown as follows: 

1. Software Method: 


Figure 6-23 : Key-Scan Flowchart (1) 


Version 1.3 




Key-Scan_Enable ( ); // KSCR Bit-7 is set to 1 

while (1) 

{ 


// Check Key-Scan status 

KS_Sta = LCD_DataRead ( ); 

KS_Sta = KS_Sta & 0x02; 

If ( KS_Sta ) 

{ 

LCD_CmdWrite ( KSCR2 ); // Read Key Press Number 

KeyNum = LCD_DataRead ( ); 

Switch(KeyNum) 

{ 

Case 0: 

// Key release 

Case 1: 

LCD_CmdWrite ( KSDR0 ); // Read Key Code0 

KeyCode1 = LCD_DataRead ( ); 

// Do corresponding event 

Case 2: 






Case 3: 








} 

} 

} 


temp = LCD_DataRead ( ); 

temp = temp & 0xfd; 



// Clear Key-Scan status 


Version 1.3 



2. Hardware Method: 


Figure 6-24 : Key-Scan Flowchart (2) 


Version 1.3 




Key-Scan_Enable ( ); 

// Set Reg. KSCR1 Bit-7=1 

Key-Scan_INT_Mask_Enable ( ); 

// Set Reg. INTR Bit-5=1 

: : 

Execute other functions 

// Jump to ISR when external interrupt 

: 

Int EXT_INT_Service_Routine // ISR entry 

{ 




} 


{ 

LCD_CmdWrite ( KSCR2 ); 

KeyNum = LCD_DataRead ( ); 

Switch(KeyNum) 

{ 

Case 0: 

// Key release 

Case 1: 

LCD_CmdWrite ( KSDR0 ); 



Case 2: 






Case 3: 








} 


temp = LCD_DataRead ( ); 

temp = temp & 0xfd; 



} 

else if (INT_Sta & 0x01) 

{ 

: 

} 

else if (INT_Sta & 0x04) 

{ 

: 

} 


// Read Key Press Number 

// Read Key Code0 






// Clear Key-Scan status 

// Check if Touch Panel interrupt 



Version 1.3 



6-6 Clock and Reset 

RA8806 supports internal or external clock source without extra select pin. 

6-6-1 OSC Circuit 

RA8806 contains a built-in OSC circuits. It generates corresponding clock by connecting an external 

4M ~ 12MHz crystal between XG and XD pins. Figure 6-25 is the clock circuit for X’tal oscillator and 

external clock. 



15pF 

15pF 

X’tal 

(4~12MHz) 

XG 

XD 

CLK 

(4~12MHz) 

XG 

XD 

Figure 6-25 : Clock Circuit 

6-6-2 External Clock 

RA8806 can also accept external clock for system clock source. The external clock source can 

directly connect to XG pin, and XD pin must be kept floating. 

tRCL 

tFCL 

EXT¢0 

tWL 

tWH 

Figure 6-26 : External Clock 

tC 

Table 6-18 : Clock Timing Ta = –20 to 75℃ 

Signal Symbol Parameter 

V DD = 5V V DD = 3.3V 

Min. Max. Min. Max. 

Unit 

t RCL External clock rise time — 10 — 10 ns 

t FCL External clock fall time — 10 — 10 ns 

EXT Φ0 t WH 

External clock 

HIGH-level pulse width 

Note 1. Note 2. Note 1. Note 2. ns 

t WL 

External clock 

LOW-level pulse width 

Note 1. Note 2. Note 1. Note 2. ns 

t C External clock period 66.6 — 83.3 — ns 

Notes: 

475 

1. ( t C − tRCL 

− tFCL 

) × < t WH, 

t WL 

1000 

525 

2. ( t C − tRCL 

− tFCL 

) × > t WH, 

t WL 

1000 

Condition 


Version 1.3 



6-6-3 Reset 

The RA8806 requires a reset pulse at least 1024*tc long after power-on in order to re-initialize its 

internal state. If the oscillator frequency is 6Mhz, then the Reset pulse is at least 170.7µs. For 

maximum reliability, it is not recommended to apply a DC voltage to the LCD panel while the 

RA8806 is reset. Turn off the LCD power supplies for at least one frame period after the start of the 

reset pulse. 


VDD 


100KΩ 

From MCU 

ZRST 

1uF 

ZRST 

0.1uF 

SW 

(Option) 

(1) (2) 

Figure 6-27: Examples of ZRST Pin 

Figure 6-27 is an example for ZRST application circuit. It could be controlled by MPU such as (1) of 

Figure 6-27. Or, generated by a RC circuit such as (2) of Figure 6-27. 

The RA8806 cannot receive commands while it is reset. Commands to initialize the internal registers 

should be issued soon after a reset. During reset, the LCD drive signals XD, LP and FR are halted. 

A delay of 1ms (minimum) is required following the rising edges of both ZRST and VDD to allow for 

system stabilization. Please refer to Figure 6-28 for more detail description. 

0.8VDD 

t RS 

t RH 

VDD 

Reset Complete 

ZRST 

0.8VDD 

0.2VDD 

t RST 

Max. 

Typ. 

Min. 

Unit 

t RS 

Reset setup time 

-- 

-- 

1 

ms 

t RH 

Reset hold time 

-- 

-- 

1 

ms 

t RST 

Reset active time 

-- 

-- 

1024 

t c (*) 

*t C is the period of system clock, 

for example: 10MHz, t C = 100ns 

Figure 6-28: Reset Timing 


Version 1.3 



6-7 Power 

6-7-1 Power Architecture 

The power architecture of RA8806 is shown as Figure 6-29. VDDP, GNDP are I/O powers and 

AVDD, AGND are analog powers for internal ADC. There is an embedded 5V-to-3V DC/DC 

Converter which is without any external controlled pin. The application circuits of 5V and 3V system 

will be described below. 


VDDP 

Core 

GNDP 

VDD 

VDDH 

AVDD 

5V 3V 

ADC 

GND 

AGND 

Figure 6-29 : Power Architecture 

6-7-2 3V Application Circuit 

When RA8806 operates in 3V system, the power consumption will be smaller. The Figure 6-30 is 

the example for 3V system. Users need to connect 3V power to VDDP, VDD and AVDD respectively. 

The DC/DC Converter is not used, so VDDH needs to be kept floating. 

3.3V 

MCU 

3.3V 


VDD 

0.47uH 

(Option) 

VDDP 

VDD 

VDDH 

0.47uH 

(Option) 

AVDD 

GNDP 

10u 0.1u 0.1u 0.1u 

GND 

GND 

I/O 

MCU I/F 

AGND 

Figure 6-30: The Power Connection of 3V 


Version 1.3 



6-7-3 5V Application Circuit 

When RA8806 operates in 5V system, 5V power inputs from VDDH and 3V power will output at 

VDD that is the power to supply internal core. Users need to add 1µF and 0.1µF capacitors in 

parallel at VDD to increase power stability. 

Please note that DC-to-DC converter will increase some power consumption. So, if the RA8806 

enter Sleep mode then it will keep around 20µA static current. 

5V 

MCU 

5V 


VDD 

~3V 

VDDP 

VDD 

VDDH 

0.47uH 

(Option) 

AVDD 

GNDP 

GND 

I/O 

10u 0.1u 1u 0.1u 0.1u 

MCU I/F 

GND 

AGND 

Figure 6-31 : The Power Connection of 5V 


Version 1.3 



6-7-4 Sleep Mode 

The RA8806 provide two operation modes: Normal mode and Sleep mode. Please refer to Chapter 

5 “Register Description” for Register WLCR explanation. RA8806 will shut down the system clock, to 

achieve the minimum power consumption. When RA8806 is under the Sleep mode, only the status 

register can be read, other registers are not allowed to read. Other command besides REG[00h] Bit- 

7(Sleep mode) can’t be written. When RA8806 is under Sleep Mode, it can accept the following 

three methods to wake-up. 

1. Write REG[00h] Bit-7 = 0, then it will return to Normal Mode. 

2. Touch event is detected. 

3. Key-Scan is detected. 

When RA8806 quit from Sleep mode, to avoid the incorrect activity, RA8806 must de-bounce the 

wake-up event for enough time(about 1,000 system clock periods) to make sure it, then quit from 

Sleep mode. 

Besides, when MPU program RA8806 to enter Sleep mode, RA8806 can’t receive command from 

MPU anymore till quit the Sleep mode. The command will be lost. User program must avoid the 

possibility of the condition. For example, if RA8806 be programmed to Sleep mode, at the same 

time, the MPU receives an external interrupt, and cause the MPU enter the Interrupt Service 

Routine(ISR). That will cause RA8806 can’t correctly receive and recognize the command. 

From the view of hardware design, the condition can’t be prevented. Because the external interrupt 

is an individual mechanism of MPU. We can’t predicate the happen of it from the role of RA8806. It’s 

a possible risk even the possibility is rare. 

So it’s suggested that MPU must be mask the interrupt for RA8806 before commanding the RA8806 

to enter the Sleep mode. The interrupt mask is off after RA8806 quit from Sleep mode. Besides, 

because the status register can be read normally at Sleep mode. Also user can check the status in 

the ISR for judgment. If RA8806 is checked under Sleep mode, MPU can quit ISR and execute 

nothing to prevent incorrect activity. 

Table 6-19 


WLCR Bit 7 Normal mode and Sleep mode 

selection. 

REG[00h] 


Version 1.3 



6-8 Interrupt and Busy 

The RA8806 provides an interrupt output (INT) for MPU to indicate the status of RA8806. And a busy 

output to indicate the RA8806 is in busy state. Both signals could be set to active high or active low by 

register. 

6-8-1 Interrupt 

RA8806 provides an Interrupt signal (INT) for following event: 

 

 

 

Touch Panel touched event is happen. 

Key-Scan enable and key is pressed 

Wake-up event occurs when Sleep mode. 

These interrupt events can be masked or active respectively. It is controlled by the REG[0Fh], the 

mask and status registers. 

Besides, RA8806 also provide a software access interrupt function. When user system don’t support 

hardware interrupt signal, they can use polling method to achieve the software interrupt. 

To access hardware interrupt, user needs to set corresponding Interrupt Mask bit to 1(Refer to 

register INTR). The steps are: 

 

 

 

RA8806 generate the interrupt signal to MPU. 

After finishing the current instruction, MPU hardware will jump the PC(Program counter) 

to Interrupt Service Routine(ISR). 

In the same time that RA8806 generate the interrupt, the interrupt status is set 

to ”1”(REG[0Fh] Bit[2:0]). (For example, if key-scan interrupt activates, the Key-Scan 

status will be set to 1). 

To apply the software interrupt method, users don’t need extra setting. Just reading the status bit of 

register INTR to check the interrupt event. BTW, interrupt mask can only disable the hardware 

interrupt, but can’t disable the status of INTR. 

Example-1: 

The Figure 6-32 is an example of INT timing for Wake-up event. RA8806 provides three wake-up 

event. Please refer to Section 6-7-4 “Sleep Mode” for the detail. 

t INTST 

Wake-Up 

Event 

INT 

Figure 6-32: Interrupt Timing(1) 


Version 1.3 



t INTST = Clock Stable Time + 1024*t C 

If user use a 6MHz X’tal for system clock, the Clock Stable Time is about 3~3.5ms and t C is 167ns. 

Example-2: 

The Figure 6-33 is an example of INT timing for Key-Scan event. 

t INTST 

Key-Scan 

Event 

INT 

Figure 6-33 : Interrupt Timing(2) 

t INTST = De-bounce Time + t CKEY 

The “De-bounce Time” is set by REG[A0h] Bit[5:4], and the t CKEY is the Key-Scan Cycle that 

depends on the setting of REG[A0h] Bit[2:0]. 

Additionally, because the status bit will not be cleared to 0 automatically. So user must manually 

clear it after processing the interrupt routine. 

6-8-2 Busy 

The RA8806 also provides a “BUSY” signal. When Busy Flag is “1”, which means RA8806 is in busy 

state that RA8806 couldn’t access data from DDRAM. Two busy conditions are provided. One is 

Scan Busy and another is Memory Write Busy. The detail explains is as follows. 

Scan Busy: 

When LCD panel displays, RA8806 scan circuit will access the DDRAM. If another DDRAM access 

cycle happens. It will cause the data lose in one of them. So when scan circuit is active, it causes a 

busy condition, called Scan Busy. Figure 6-34 shows the data flow diagram of scan circuit and MPU 

memory access cycle. Figure 6-35 is same as Figure 6-15 to show RA8806 scan waveform. It 

describes the condition that RA8806 scan the display for each COM line. The COM scan time is 

combined with an Idle time and a Scan time. The Idle time period can be set by register ITCR. The 

Scan period is the time of Scan Busy. Also accessing data at Scan Busy time will cause the scan 

data lose. But it will not cause a fatal error. The scan data lose will cause the display defect. But if 

it’s not too frequent, the defect will not infect the display too much. 


Version 1.3 




Display 

Data RAM 

Memory-Write 

LCD-Scan 

MCU 

Interface 

Controller 

LCD 

Driver 

Figure 6-34 : Data Flow of DDRAM 

XCLK 

LP 

ITCR 

COM_SCAN 

T_COM 

Figure 6-35 : Scan for Each COM Line 

Memory Write Busy: 

Following two conditions will cause the Memory write busy: 

1. When MPU write data in text-mode. Depending on different size of font, it needs an enough 

time to write the font to DDRAM. At the period, RA8806 can’t access the DDRAM again, it’s 

a memory write busy condition. 

2. When MPU program RA8806 as a memory clear function(FNCR Bit-3 = 1). The period of 

clear DDRAM also cause a memory write busy. 

It will cause the DDRAM lost when accessing DDRAM in the period of Memory Write Busy. So user 

must check the busy status after the upper two conditions is done. 

Besides, RA8806 provide polarity setting for “BUSY” and interrupt “INT” pin. (Please refer to register 

MISC) 

Normally, this “BUSY” pin is connected to MPU I/O input, and then MPU have to monitor this pin 

before accessing RA8806. The following is the timing of BUSY pin. The BUSY can be active high or 

low that depend on the setting of REG[01h] Bit-5. 


Version 1.3 



RS, ZCS1 

t BST 

ZWR 

DATA[7:0] 

(Write) 

BUSY 

t BUSY 

Figure 6-36 : BUSY Timing Chart 

Table 6-20 : Busy Timing 

Signal Symbol Parameter 

Rating 

Min Max 

Unit 

Condition 

BUSY 

t BST 

t BUSY 

Busy Setup Time 

Busy Active Time 

Half Size Font 150 -- ns 

Full Size Font 250 

Half Size Font -- 50*t c ns 

Full Size Font -- 100*t c ns 

System Clock: 

8MHz 

VDD: 5V 

t c = 125ns 


Version 1.3 



6-9 PWM 

RA8806 provide a set of programmable PWM (Pulse Width Modulation) for LCD contrast adjustment. 

The PWM frequency and duty can be set by register. And the driving capability of PWM output pin is 

larger than other output pin, about 4 multiples of normal output. Besides, if the PWM function is disable, 

it can use as normal IO signal. The relative function setting please refers to the table below. 

Table 6-21 


PCR 

Bit 7 PWM function enable 

Bit [3:0] Clock source divide ratio select 

REG[D0h] 

PDCR Bit [7:0] PWM Duty Cycle Select REG[D1h] 

The following are two examples for the PWM output (pin “PWM_OUT”): 

T PWM 

T H 

T L 

Example-1: 

System Clock = 10Mhz, 

Register PCR Bit[3:0] = 0001b Clock Source = 10MHz/2 = 5MHz 

T PWM = 256*(1/5MHz) = 51.2µs 

Register PDCR Bit[7:0] = 0Fh 

T H = 16*(1/5MHz) = 3.2µs 

T L = (256-16) * (1/ 5MHz) = 48µs 

T PWM 

T H 

T L 

Example-2: 

System Clock = 10Mhz, 

Register PCR Bit[3:0] = 0010b Clock Source = 10MHz/4 = 2.5MHz 

T PWM = 256*(1/2.5MHz) = 102.4 µs 

Register PDCR Bit[7:0] = 7Fh 

T H = 128*(1/2.5MHz) = 51.2µs 

T L = (256-128) * (1/ 2.5MHz) = 51.2µs 

Figure 6-37 : PWM_OUT Pulse 


Version 1.3 



Figure 6-38 shows the reference circuit of PWM contrast application for positive VLCD voltage. Figure 

6-39 shows the reference circuit for negative VLCD voltage. 

Figure 6-38 : PWM Reference Circuit for Positive VLCD 

Figure 6-39 : PWM Reference Circuit for Negative VLCD 


Version 1.3 



6-10 Display Function 

6-10-1 Character/Graphic Mode 

There are two modes for MPU to write data to RA8806, i.e., character mode and graphic mode. In 

graphic mode, data is written directly to DDRAM in bit-map format. In character mode, data is 

written in code format, the font bit-map in the CGROM will be written to DDRAM by this way. 

RA8806 stores two different sizes of characters in its font ROM - 1) half size font(8x16 pixels), 2) full 

size font(16x16). Figure 6-40 shows the examples. 

16X16 font 8X16 font 

Figure 6-40 : Full Size and Half Size Font 

6-10-1-1 Graphic Display 

The RA8806 graphics mode is use bit map to fill the data on the DDRAM. The Figure 6-41 is an 

example to show how to set graphics mode. 

1. Setup Register WLCR, TEXT_MD = 0 

2. Write bit map to Display Data Memory directly. 

Figure 6-41 : Graphics Mode 

The RA8806 support maximum resolution is 320x240 pixels, therefore it need 9.6Kbyte(320x240/8 = 

9600) Display Data RAM(DDRAM) to store each pixel data. Figure 6-42 is an example to show the 

DDRAM data mapping to the LCD panel. 


Version 1.3 



D7 D6 D5 D4 D3 D2 D1 D0 

1 1 1 0 0 1 1 0 

Segment 

0 1 2 3 4 5 6 7 ….. 

Display Data RAM 

Display On LCD 

Figure 6-42 : The Mapping of Display Data to LCD Panel 

The RA8806 provide an Auto-Write feature to fill a data to all of the DDRAM. At first, user writes the 

data to Register PNTR then initials the Auto-Write function(Register FNCR Bit-3). RA8806 will fill the 

data to DDRAM in very short time. Normally this feature is used to clear screen or want to fill fixed 

pattern or background on screen. 

Table 6-22 


WLCR Bit 3 Text Mode Selection REG[00h] 

6-10-1-2 Half Size Font 

RA8806 built in 4 half-size font blocks, each block contains 0h ~ FFh(256) characters, and could be 

selected by register REG[F0h] Bit[1:0]. By setting the REG[F0h] Bit[1:0], the corresponding table is 

selected. About the font table, please reference Appendix C. The RA8806 also supports ISO8859 

standard (ISO - International Organization for Standardization). Which can fully supports most Latin 

characters set. REG[F0h] Bit-7 is the option of RA8806 default coding or ISO8859 mode. In this 

mode, RA8806 internal ASCII table1 ~ 4 is mapping to the coding of ISO8859-1 ~ ISO8859-4. 

Table 6-23 


Bit 7 

ISO8859 mode 

FNCR 

Bit 2 

ASCII Mode Enable 

REG[F0h] 

Bit [1:0] 

ASCII Blocks Select 


Version 1.3 



6-10-1-3 Full Size Font 

There are three types of CGROM in RA8806, i.e. RA8806-S, RA8806-T and RA8806-J. RA8806-S 

contains the Simplified Chinese characters with the coding of GB standard. RA8806-T contains the 

Traditional Chinese characters with the coding of BIG5 standard. RA8806-J contains the JIS 

Japanese Kanji Level 1 & 2 font characters. About the detail, please refer the Appendix D, Appendix 

E, and Japanese Kanji font code table (RA8806_DS_V12_Font_JIS.pdf). 

Table 6-24 


WLCR Bit 3 Text Mode Selection REG[00h] 

The RA8806 displays the Chinese characters in text mode. Key in the Chinese code (GB or BIG5 

code) directly , then it will display the Chinese characters in cursor position. If display Chinese , 

RA8806-S accepts the GB code, RA8806-T accepts the BIG-5 code. The Chinese character 

occupies two Byes, hence the MPU should write the Chinese code (High Byte & Low Byte) separate 

into RA8806 in case the MPU interface is 8-Bit. The English code or numeric code occupies only 

one Byte, hence it will write the code into the RA8806 at a time. i.e. for RA8806-T, the BIG-5 code of 

character ” 世 ” is “A540”, MPU will send the “A5” and “40” in proper order to RA8806-T, then it will 

display the Chinese character of ” 世 ”. 

If use the Japanese Kanji font version of RA8806, that is RA8806-J, it should transfer the JIS code 

for a start , then the MPU send the code to RA8806-J. Firstly, add 80h to the Hi-Byte of JIS code, 

then to judge the Low-Byte, if it is larger or equal to 60h, then adds 40h, otherwise adds 20h. Then it 

will display the Japanese Kanji font if the new code sends to RA8806-J by MPU. i.e. the JIS code of 

character ” 粟 ” is “3040”, to transfer to the new code is “B060”, to send the “B0” and “60” in proper 

order, then it will display the Japanese Kanji font of ” 粟 ”. 

The Font ROM of RA8806-J mainly refer to the coding of JIS code, if the user use Shift-JIS code 

(called for short S-JIS), then it should be transfered by another procedure, firstly, transfer S-JIS 

code to JIS code. It is in common use of S-JIS coding for Japanese computer system, because it 

contains the full font and half font of Latin character, Hiragana, Katakana, notation and the 

Japanese Kanji font. It is named by Shift_JIS, for put in full font, to avoid put in the 0xA1~0xDF of 

the Half-width Katakana. 

The Figure 6-43 is the flow chart for the S-JIS code transfers to JIS code and JIS code transfers to 

RA8806-J, furthermore the attachment is the program for the user to refer. i.e. the S-JIS code of 

character ” 粟 ” is “88BE”, transfers to JIS code is “3040”, as the description above, JIS transfers new 

code to “B060”, then send “B0” and “60” in proper order to RA8806-J, it will display the Japanese 

Kanji font of ” 粟 ”. i.e. the character ” 甌 ” of J-JIS code is “E14D”, transfers to JIS code is “612E”, as 

the mention above, the JIS transfer new code to “E14E”, then send “E1” and “4E” in proper order to 

RA8806-J, in the meantime display the Japanese Kanji font of ” 甌 ”. 


Version 1.3 



SJIS-High Byte 

SJIS-Low Byte 

81h ~ 9Fh 

E0h ~ FFh 

40h ~ 7Eh 

80h ~ 9Eh 

9Fh ~ FCh 

-81h -C1h 

-01h 

00h ~ 2Eh 

40h ~ 9Dh 

左移 1 bit 

+ N 

-1Fh 

-7Eh 

00h ~ 5Dh 

+21h 

21h ~ 7Eh 

(JIS-High Byte) 

N=0 N=1 

21h ~ 7Eh 

(JIS-Low Byte) 

+80h If >=0x60 If < 0x60 

+40h 

+20h 

A1h ~ FEh 

(RA8806 ROM Code-High Byte) 

A0h ~ BEh / 41h ~ 7Fh 

(RA8806 ROM Code-Low Byte) 

Figure 6-43 : The flow chart of the S-JIS code transfer to RA8806-J 

//=================================================== 

// Main Program 

//=================================================== 

void main(void) 

{ 

LCD_Reset(); 

LCD_Initial(); 

LCD_ON(); 

LCD_Clear(); 

LCD_Text(); 

// Turn on the screen 

// Clear display memory all 

// Switch display mode to “Text mode” 

LCD_GotoXY(0, 0); 

LCD_Print_J_Str(SJIS_string, 20); 

} 

// SJIS_string is a string include Shifit - JIS Code 

//=================================================== 

// Subroutine : Transform SJIS to JIS 

//=================================================== 

void LCD_Print_JIS_Str(uchar *ptr, int char_num) // string pointer , char numbers 

{ 

int temp = 0; 

unsigned char SJIS_HB, SJIS_LB, JIS_HB, JIS_LB, LSB; 


Version 1.3 



while(temp < char_num) 

{ 

if(ptr[temp] = 0x9F) 

{ 

JIS_LB = SJIS_LB - 0x7E; 

LSB = 0x01; 

} 

else if(SJIS_LB = 0xE0) 

{ 

SJIS_HB = SJIS_HB - 0xC1; 

} 

else if(SJIS_HB

Version 1.3 



} 

} 

} 

LCD_DataWrite(JIS_HB); 

LCD_DataWrite(JIS_LB); 

6-10-1-4 Bold and Inverse 

The RA8806 supports the bold and inverse font. The user only needs to set up the related register 

bit that before send the character code to RA8806. Figure 6-44 shows the examples. 

16X16 inverse font 

8X16 inverse font 

16X16 bold font 

8X16 bold font 

Figure 6-44 : Inverse and Bold Font Example. 

Table 6-24 


Bit 3 

Text Mode Selection 

WLCR 

Bit 2 

Bit 1 

Set Display On/Off Selection 

Blink Mode Selection 

REG[00h] 

Bit 0 

Inverse Mode Selection 

WCCR Bit 4 Bold Font (Character Mode Only) REG[10h] 


Version 1.3 



6-10-1-5 Two Layer Display 

The RA8806 embedded two DDRAM for two layers display. The register MAMR is used to show the 

visible display for DDRAM1 and DDRAM2. It provides six display modes: 

Display DDRAM1 

Display DDRAM2 

Display DDRAM1 OR DDRAM2 

Display DDRAM1 XOR DDRAM2 

Display DDRAM1 NOR DDRAM2 

Display DDRAM1 AND DDRAM2 

Please refer Figure 6-45 and Register description of MAMR Bit[6:4] and Bit[3:2]. 

DDRAM1 

DDRAM2 

Visible Display 

1 

Controller 

OR 

Controller 

2 

Controller 

NOR 

Controller 

3 

Controller 

XOR 

Controller 

4 

Controller 

AND 

roller 

Figure 6-45 : Two Layers Display 

Table 6-25 


MAMR 

Bit [6:4] 

Bit [3:2] 

Display Layer Selection 


REG[12h] 


Version 1.3 



6-10-1-6 Line Gap 

The RA8806 provide Line Gap feature. Especially in Chinese display, if add some space in each line 

will look better. The range of line gap is 1 ~ 16 pixel. Once the line gap is setup, the cursor will 

automatically move to property position for each line. 

Setting the low nibble of the register CHWI, user can adjust the line gap. To deserve to be 

mentioned, when RA8806 operating in 90 degree mode, the line gap is either 0 pixel or 8 pixels, no 

matter what the font size. The selection of two conditions is according to Bit-3 of the register CHWI. 

Table 6-26 


CHWI 

Bit [7:4] 

Bit [3:2] 

Set Cursor Height 

Set Line Gap 

REG[11h] 

6-10-2 Gray Scale Display 

The RA8806 also provide 4-gray-scale display implemented by FRC method. In gray level display 

mode, RA8806 combines the data of DDRAM1 and DDRAM2 as a gray picture. Each gray pixel 

occupies 2 bits of DDRAM data for display. Data [00b] indicate an empty pixel display and [11b] is 

solid display. [01b] & [10b] will be time sharing as 1/3 and 2/3 lightness. Please refer to Figure 6-46. 

7 6 5 4 3 2 1 0 

7 6 5 4 3 2 1 0 

Gray-Scale Display 

3a 3b 2a 2b 1a 1b 0a 0b 

3a 3b 2a 2b 1a 1b 0a 0b 

7a 7b 6a 6b 5a 5b 4a 4b 

7a 7b 6a 6b 5a 5b 4a 4b 

DDRAM2 

DDRAM1 

Bit-a 

Bit-b 

Gray-Level 

0 

0 

1 

1 

0 

1 

0 

1 

1 

2 

3 

4 

DDRAM1: Display Data RAM #1 

DDRAM2: Display Data RAM #2 

In Gray-Scale mode, both DDRAM are used. 

Figure 6-46 : Mapping Rule of 4-Gray-Scale Display 

According to the data write order, RA8806 support 2 data input methodology for Gray-Scale display. 

User can write the data as the same way of mono graphic display. 

1. Horizontal moving first then Vertical, refer Figure 6-47. 

2. Vertical moving first then Horizontal, refer Figure 6-48. 


Version 1.3 



Horizontal-Write (Panel Resolution: 320 x 240) 

1st byte 

2nd byte 

3rd byte 

40th byte 

41th byte 

42th byte 

43th byte 

80th byte 

81th byte 

82th byte 

83th byte 

120th byte 

N+1th byte 

N+2th byte 

N+3th byte 

N+40th byte 

Figure 6-47 : Horizontal Write 

1st byte 

2th byte 

3rd byte 

Vertical-Write (Panel Resolution: 320 x 240) 

241nd byte 

242th byte 

243th byte 

Nth byte 

N+1th byte 

N+2th byte 

240th byte 

480th byte 

N+240th byte 

Figure 6-48 : Vertical Write 

About the register setting, please refer to following register: 

Table 6-27 


MAMR 

Bit 7 

Bit [6:4] 

Cursor Auto Shifting Direction 

Gray Mode selection 

REG[12h] 


Version 1.3 



The picture below is an example of 4-gray-level picture, the program example are attached below it: 

Figure 6-49 : 4-Gray-Scale Example 

Program Example: 

LCD_Graphic(); 

// Set graphic mode 

Gray_Mode(); 

// Set REG[12h] Bit[6:4] to 000b, as gray level display 

Scan_Diret_H_V(); 

// Set REG[12h] Bit-7 to 0, Cursor moves from left to right 

LCD_GotoXY( 0 , 0 ); 

LCD_CmdWrite( 0xB0 ); // Write memory command 

for ( i = 0 ; I < 4800 ; i++ ) // Write data 

{ 

LCD_DataWrite( 0x00 ) ; // Gray Level 1 ( 00 ) 

} 

for ( i = 0 ; I < 4800 ; i++ ) 

{ 

LCD_DataWrite( 0x55 ) ; // Gray Level 2 ( 01 ) 

} 

for ( i = 0 ; I < 4800 ; i++ ) 

{ 

LCD_DataWrite( 0xAA ) ; // Gray Level 3 ( 10 ) 

} 

for ( i = 0 ; I < 4800 ; i++ ) 

{ 

LCD_DataWrite( 0xFF ) ; // Gray Level 4 ( 11 ) 

} 


Version 1.3 



6-10-3 Font Size Adjustment and Font Write-Time 

RA8806 supports Font size adjustment. There are two types of characters stored in RA8806 font 

ROM - Half size (8x16 pixels) and full size (16x16 pixels) characters. The“ Font size adjustment” 

function supports the font enlargement from 1 to 4 times bigger in vertical and horizontal respective 

directions. Programmer can adjust the character size from setting FVHT[7:4] : 

Table 6-28 


FVHT 

Bit [7:6] 

Bit [5:4] 

Horizontal width adjustment for character 

Vertical width adjustment for character 

REG[F1h] 

Figure 6-50 shows the example of character enlargement: 

2x1 enlarged 8x16 font 

1x2 enlarged 16x16 font 

Figure 6-50 : Font Size Adjustment 

Additionally, the Font Sized Adjustment is not only available for the character display mode, but also 

for the following display modes: 

For displaying the user created fonts 

90° font and display rotation 


Version 1.3 



After writing completed font code(One byte for half size font and two bytes for full-size font), it will 

takes an enough time for data to be written into the DDRAM. In the mean while no data can be read 

or wrote into DDRAM. (Please refer to Section 6-8 “Interrupt and Busy”, the description of “Memory 

Write Busy”). The writing time is differing from the enlargement multiplier of font size. Its calculation 

formula is as follows : 

T fw = ( 16*tc + 32*tc x ( HW x VH ) ) x ( 1 + 10% ) 

T fw : Font Write time 

tc : System clock period 

HW : Horizontal enlargement multiplier. 

VH : Vertical enlargement multiplier. 

Here 10% is for the flexible error consideration. Please refer to the following examples: (Estimate 

the system clock is 4MHz and the tc is 250ns) 

Table 6-29 : Delay Time for Font Enlargement 

Font enlargement multiplier Standard delay time(μS) Suggested delay time(μS) 

1 x 1 12 13.2 

2 x 2 36 39.6 

3 x 3 76 83.6 

4 x 4 132 145.2 

In addition to calculate writing time and delay, programmer can also check the “Busy” status to know 

if font characters were written into the DDRAM. Please refer to the “ Status Register” for the 

description of “Busy”. 


Version 1.3 



6-10-4 Font Vertical Display 

RA8806 features of its “Font Vertical Display” function. This function enables the normal display 

change to vertical display. This means the original 320x240 panel can be used as a 240x320 panel 

to display embedded character font or data in vertical way, and no need to change scan direction or 

the LCD driver layout. The LCD panel could display from both vertical and horizontal ways. This 

function is option on setting the Bit-3 of register WCCR. When WCCR Bit-3 =1 (Font Rotation Mode), 

the font character will be written in vertical display. Figure 6-51 shows the example of font vertical 

display. 

0 

0 7 

0 15 

0 

15 

7 

Vertical Display 

Normal Display 

Figure 6-51: Font Vertical Display Function 

Under the vertical display mode, the cursor moves from the direction of up to down. And the cursor 

display is also differing to normal display mode. (Please refer to Section 6-13-4 “Cursor Width and 

Height” for detail descriptions). 

Due to the advance rotate function, if user chose a 240x160 module, then it will be very easy to use 

same module but as an 160x240 module. The following Figure 6-52 shows the example of 320x240 

panel rotate to as 240X320 application. In normal mode, if write text font “RAIO” then the screen 

show as (1) of Figure 6-52. If set the T90DEG(Bit-3 of REG[10h]) = 1 and CDIR(Bit-0 of REG[01h]) 

= 1 first, then write text font “RAIO”, the screen will show as (2) of Figure 6-52. 

SEG0 

COM0 


SEG319 

COM239 

SEG0 


COM0 

COM239 

(1) 320x240 for Normal use 

SEG319 

(2) As a 240x320 Application 

T90DEG = 1 , CDIR = 1 

Figure 6-52 : Font Display in Rotate Mode 


Version 1.3 



The relative register list about font rotation function is: 

Table 6-30 


WCCR Bit 3 Font rotation mode enable REG[10h] 

MISC Bit 0 COM direction selection REG[01h] 

Besides the cursor display function, the other functions in the font rotation mode work as the same 

behavior as normal mode, including: 

1) Font enlargement function 

2) Full alignment function 

3) Line Gap adjustment function 

4) Scroll function 


Version 1.3 



6-11 User-Defined Font 

The RA8806 embedded a 512Byte CGRAM for user to create new character. The user could create 

font, special symbol or pattern in this memory. If user only uses one DDRAM, then the other one could 

also use as CGRAM. 

Therefore, the RA8806 provides 3 regions for user to create new character(symbol or pattern) as 

following: 

1. 512 Bytes CGRAM 

2. 9.6K Bytes DDRAM1 (When user only shows DDRAM2 data on screen) 

3. 9.6K Bytes DDRAM2 (When user only shows DDRAM1 data on screen) 

Table 6-31 : Font Code for User-Created 

Region Size Code and Range Capacity 

CGRAM 

512 bytes 

Half-Size : 8F00h ~ 8F1Fh 

Full-Size : 9F00h ~ 9F0Fh 

32 Half-Size chars 

16 Full-Size chars 

DDRAM1 

9.6 Kbytes 

Half-Size : 8000h ~ 8E27h 

Full-Size : 9000h ~ 9E13h 



DDRAM2 

9.6 Kbytes 

Half-Size : 8000h ~ 8E27h 

Full-Size : 9000h ~ 9E13h 



6-11-1 Create Font in CGRAM 

The CGRAM is a 512Byte RAM, so it could create 32 Half-Size or 16 Full-Size characters. The 

Table 6-32 is the font code mapping table in CGRAM. Note the font codes were fix in RA8806. And 

the Font# was defined in Bit[3:0] of REG[CURY]. 

Table 6-32 : CGRAM Font Code Mapping Table 

Font# 

Code 

0 

1 

2 

3 

4 

5 

6 

7 

Half-Size 

8F00 8F01 8F02 8F03 8F04 8F05 8F06 8F07 8F08 8F09 8F0A 8F0B8F0C8F0D8F0E 

8F0F 

Full-Size 

9F00 

9F01 

9F02 

9F03 

9F04 

9F05 

9F06 

9F07 

Font# 

Code 

8 

9 

10 

11 

12 

13 

14 

15 

Half-Size 

8F10 8F11 8F12 8F13 8F14 8F15 8F16 8F17 8F18 8F19 8F1A 8F1B8F1C8F1D8F1E 

8F1F 

Full-Size 

9F08 

9F09 

9F0A 

9F0B 

9F0C 

9F0D 

9F0E 

9F0F 


Version 1.3 



7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 

7 6 5 4 3 2 1 0 

0000 

0001 

0010 

0011 

0100 

0101 

0110 

0111 

1000 

1001 

1010 

1011 

1100 

1101 

1110 

1111 

0000 

0001 

0010 

0011 

0100 

0101 

0110 

0111 

1000 

1001 

1010 

1011 

1100 

1101 

1110 

1111 

(1) Full-size Font (2) Half-size Font 

Figure 6-53 : Example of Created Font Bit-map Data 

According to the user-created font register setting in CGRAM, please refer to the below table. 

Table 6-33 : Register Definition for Created-font in CGRAM 


MAMR 

Bit 7 

Bit [6:4] 

Bit [1:0] 

Cursor Increase enable 

Display mode 

Select memory for write cycle 

The Bit[4:0] is the address for writing 

bit-map data of create font. When 

CURX Bit [4:0] create a full-size font, normally set to 

0. When create an odd half-size font, 

normally set to 0, and set 10h for 

even font. 

CURY Bit [3:0] Indicate which font code data will be 

created. 

REG[12h] 

REG[60h] 

REG[70h] 


Version 1.3 



CGRAM 

Create Font 

Set MAMR to access 

CGRAM 

Set display data is 

DDRAM1 or DDRAM2 

Set the CURX to 0(First 

byte in font) 

Write memory write command 

(B0h) and write the font data 

sequentially. (*2) 

Set CURY 

(It indicates which font will 

be created) (*1) 

Write the corresponding code 

to show the font on active 

display layer (*3) 

Note: 

Figure 6-54 : The Flow-chart of User-created Font on CGRAM 

1. CGRAM contains 512 bytes and can contain 16 16x16 full-size or 32 8x16 half-size usercreated 

font. Each full-size font contains 32bytes. 

2. For created full-size font, after CURY is assign(0~15) and CURX is set to 0, a created-font 

bit-map can be filled by the 32 continuous memory writes cycle. And then CURY will be 

increased by 1. Please refer the following Program Example(1). The result is show (1) of 

Figure 6-53 on screen. 

3. For created half-size font, after CURY is assign(0~15) and CURX is set to 0(odd font) or 

10h(even font), a created-font bit-map can be filled by the 16 continuous memory writes cycle. 

Please refer the following Program Example(2). The result is show (2) of Figure 6-53 on 

screen. 

4. The CGRAM font code is 8F00~8F1F for Half-size font, and 9F00~9F0Fh for full-size font. 

Refer to Table 6-31. 

Program Example(1): 

// Create a full-size font in CGRAM and show on the screen. 

// font_data[] = {00, 00, 07, 1F, 20, 67, 68, 09, 1A, 15, 16, 15, 12, 1F, 00, 00, 

// 00, 00, E0, F8, 04, E6, 16, 90, 58, A8, 68, A8, 48, F8, 00, 00} 

Access_CGRAM(); 

// MAMR[1:0] = 00b 

Only_Show_DDRAM1(); 

// MAMR[6:4] = 001b 

LCD_CmdWrite( CURY ); 

// Create 6 th full-size character 

LCD_DataWrite( 0x05 ); 

LCD_CmdWrite( CURX ); 

// Write font-data from 1 st byte 


LCD_CmdWrite( MWCR); 

// B0h, Memory write command 

for( i = 0; i < 32; i++ ) 

// 32 continuous write for font bit-map 

{ LCD_DataWrite( font_data[i] ); 

Delay2us(50); 

} 

Access_DDRAM1(); 

LCD_Text(); 

LCD_GotoXY( 5 , 5 ); // Set Cursor position ( 5 , 5 ) 

LCD_CmdWrite( MWCR); // Corresponding font code( 9F05h ) 

LCD_DataWrite( 0x9F ); 


Version 1.3 



LCD_DataWrite( 0x05 ); // Show as (1) of Figure 6-53 


Version 1.3 




// Create a half-size font in CGRAM and show on the screen. 

// font_data[] = {00, 82, 44, 28, FE, 10, 10, 10, FE, 10, 10, 38, 54, 92, 10, 00} 

Access_CGRAM(); 

// MAMR[1:0] = 00b 

Only_Show_DDRAM1(); 

// MAMR[6:4] = 001b 

LCD_CmdWrite( CURY ); 

// Create 6 th half-size char 


LCD_CmdWrite( CURX ); 

// Write font-data from 1 st byte 


LCD_CmdWrite( MWCR); 

// B0h, Memory write command 

for( i = 0; i < 16; i++ ) 

// 16 continuous write for font bit-map 

{ 

LCD_DataWrite( font_data[i] ); 

Delay2us(50); 

} 

Access_DDRAM1(); 

LCD_Text(); 

LCD_GotoXY( 5 , 5 ); // Set Cursor position ( 5 , 5 ) 

LCD_CmdWrite( MWCR); // Corresponding font code( 8F05h ) 

LCD_DataWrite( 0x8F ); 

LCD_DataWrite( 0x05 ); // Show as (2) of Figure 6-53 

6-11-2 Create Font in DDRAM 

The DDRAM are 9.6KByte RAM, so it could create 600 Half-Size or 300 Full-Size characters. Table 

6-35 is the font code mapping table in DDRAM for Half-Size characters. Table 6-36 is the font code 

mapping table in DDRAM for Full –Size characters. These font codes were also fix in RA8806. The 

register CURX and CURY are used to point the address that bit-map data to create font. 

According to the register setting of user-created font in DDRAM, please refer to the below table. 

Table 6-34 : Register Definition for Created-font in DDRAM 


MAMR 

Bit 7 

Bit [6:4] 

Bit [1:0] 

Cursor Increase enable 

Display mode 

Select memory for write cycle 

REG[12h] 

CURX Bit [5:0] 

Both registers are Indicate which font 

REG[60h] 

CURY Bit [7:0] code data will be created. 

REG[70h] 


Version 1.3 



Table 6-35 : DDRAM1 and DDRAM2 Half-size Font Code Mapping 

0 

1 

2 

3 

4 

5 

6 

7 

8 

9 

CURX 

CURY 

00 

10 

20 

30 

40 

50 

60 

70 

80 

90 

0 1 2 ........................................ 26 27 

0 1 2 ........................................ 26 27 

8000 8001 8002 ........................................ 8026 8027 

8100 8101 8102 ........................................ 8126 8127 

8200 8201 8202 ........................................ 8226 8227 

8300 8301 8302 ........................................ 8326 8327 

8400 8401 8402 ........................................ 8426 8427 

8500 8501 8502 ........................................ 8526 8527 

8600 8601 8602 ........................................ 8626 8627 

8700 8701 8702 ........................................ 8726 8727 

8800 8801 8802 ........................................ 8826 8827 

8900 8901 8902 ........................................ 8926 8927 

10 

A0 

8A00 8A01 8A02 ........................................ 

8A26 8A27 

11 

B0 

8B00 8B01 8B02 ........................................ 

8B26 8B27 

12 

C0 

8C00 8C01 8C02 ........................................ 

8C26 8C27 

13 

D0 

8D00 8D01 8D02 ........................................ 

8D26 8D27 

14 

E0 

8E00 8E01 8E02 ........................................ 

8E26 8E27 

Table 6-36 : DDRAM1 and DDRAM2 Full-size Font Code Mapping Table 

0 

CURX 

0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 1415 16 17 18 19 1A1B 1C1D1E 1F 20 21 22 23 24 25 26 27 

CURY 

00 

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 

9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 9013 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

10 

20 

30 

40 

50 

60 

70 

80 

90 

A0 

B0 

C0 

D0 

E0 

9100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 9113 

9200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 9213 

9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 9313 

9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 9413 

9500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 9513 

9600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 9613 

9700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 9713 

9800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 9813 

9900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 9913 

9A00 9A01 9A02 9A03 9A04 9A05 9A06 9A07 9A08 9A09 9A0A 9A0B 9A0C 9A0D 9A0E 9A0F 9A10 9A11 9A12 9A13 

9B00 9B01 9B02 9B03 9B04 9B05 9B06 9B07 9B08 9B09 9B0A 9B0B 9B0C 9B0D 9B0E 9B0F 9B10 9B11 9B12 9B13 

9C00 9C01 9C02 9C03 9C04 9C05 9C06 9C07 9C08 9C09 9C0A 9C0B 9C0C 9C0D 9C0E 9C0F 9C10 9C11 9C12 9C13 

9D00 9D01 9D02 9D03 9D04 9D05 9D06 9D07 9D08 9D09 9D0A 9D0B 9D0C 9D0D 9D0E 9D0F 9D10 9D11 9D12 9D13 

9E00 9E01 9E02 9E03 9E04 9E05 9E06 9E07 9E08 9E09 9E0A 9E0B 9E0C 9E0D 9E0E 9E0F 9E10 9E11 9E12 9E13 


Version 1.3 



Start 

Access DDRAM1 

( REG[12h] [1:0] = 0 1 ) 

Show DDRAM2 

N0 

Write 16 bytes data ? 

Access Page2 

( REG[12h] [1:0] = 1 0 ) 

( REG[12h] [6:4] = 010 ) 

Set Graphic Mode 

( REG[00h] B3 = 0 ) 

Yes 

X add 1 

(Set REG[60h]) 

Set Text Mode 

( REG[00h] B3 = 1 ) 

Set Cursor shifting 

Direction, vertical 

first then horizontal 

( REG[12h] B7 = 1 ) 

Set XY -axis ( X, Y ) 

( Set REG[60h],[70h] ) 

Set Cursor shifting 

Direction, horizontal 

first then vertical 

( REG[12h] B7 = 0 ) 


( Set REG[60h],[70h] ) 

Write Right-half font 

data to DDRAM1 

Y add 1 



and execute Memory 

Write CMD 

Write Left-half font 

data to DDRAM1 

Write 16 bytes data ? 

N0 

Write font data that 

already defined at 

DDRAM1 to DDRAM2 

Y add 1 


Yes 

Figure 6-55 : Flowchart of User-created font in DDRAM1 

The above flow-chart is an example to create a Full-size in DDRAM1 and show the new font on 

screen(DDRAM2). At first, user have to set up the CURX and CURY to define which code data will 

be created, and then write 32Bytes bit-map data to DDRAM1. The CURX need to set twice for each 

16Bytes data – the left and right of full-size font. Please refer the following Program Example(3). If 

we want to create a full-size font as (1) of Figure 6-53 to mapping code – 9205h in Table 6-36. The 

result is show (1) of Figure 6-53 on screen. 


Version 1.3 




// Create a full-size font in DDRAM1 and show on the screen. 

// font_data[] = {00, 00, 07, 1F, 20, 67, 68, 09, 1A, 15, 16, 15, 12, 1F, 00, 00, 

// 00, 00, E0, F8, 04, E6, 16, 90, 58, A8, 68, A8, 48, F8, 00, 00} 

Access_DDRAM1(); // MAMR[1:0] = 01 

Only_Show_DDRAM2(); // MAMR[6:4] = 010 

LCD_Graphic(); // WLCR. Bit-3 = 0 

Cursor_Shift_Direct_VH(); // MAMR. Bit-7 = 1 

// Set the cursor moving in vertical 

LCD_GotoXY(0x0A, 0x20); // Write the left part of full-size font 

LCD_CmdWrite( MWCR); // Memory write command 

for(i=0;i

Version 1.3 



6-11-3 Create Symbol 

RA8806 provides font creator function that allows user to design and create new fonts, special 

symbols or logos and store into its embedded CGRAM or DDRAM. The user-created characters 

each defined as a full-size (16x16) or half-size (8x16) character bitmap font formats, thus 24x16, 

40x16, 16x32 or bigger sized fonts are also possible to create accordingly. The following Figure 

6-56 represents a user created symbol with size 24x16. 

Figure 6-56 : A 24x16 Symbol Example 

For creating a new symbol, in addition to write command to CGRAM or DDRAM, note the setting of 

the font codes before trying to write characters to be displayed. See the following 2 examples of 

creating this 24x16 symbol in DDRAM: 

When the first address - (CURX, CURY) of data write to DDRAM is (0, 0), the font code of this symbol are 

0x8000, 0x8001 and 0x8002, as Figure 6-57 below: 

When the first address of date write to DDRAM is (2, 10h), the font code of this symbol are 0x8105,0x8106, 

0x8107 and so on. Please refer the following Program Example(4). The result is show Figure 6-56 on screen. 

Font Code:0x8105 



Figure 6-57 : Font Code of User’s Created Symbol for Program Example(4) 


Version 1.3 




// Create a 24x16 symbol in DDRAM1 and show on the screen. 

// font_data[] = {00, 02, 06, 0A, 12, 23, 40, 80, 40, 23, 12, 0A, 06, 02, 00, 00, 

// 00, 00, 00, 00, 00, FF, 00, 00, 00, FF, 00, 00, 00, 00, 00, 00, 

// 00, 80, C0, A0, 90, 88, 04, 02, 04, 88, 90, A0, C0, 80, 00, 00} 

Access_DDRAM1(); // MAMR[1:0] = 01 

Only_Show_DDRAM2(); // MAMR[6:4] = 010 

LCD_Graphic(); // WLCR. Bit-3 = 0 

Cursor_Shift_Direct_VH(); // MAMR. Bit-7 = 1 

// Set the cursor moving in vertical 

LCD_GotoXY(0x02, 0x10); // Write the left part of symbol 

LCD_CmdWrite( MWCR); // Memory write command 

for(i=0;i

Version 1.3 



especially under Rotate 90 degree and Font Enlargement mode. 

6-12 Scroll Function 

6-12-1 Horizontal Scrolling 

The RA8806 provide Horizontal Scrolling function. You can assign an area by Register BGSG and 

EDSG. Once start the horizontal scrolling, the assigned area will shift step by step and each step is 

8 pixels width. 

About Horizontal Scrolling register setting, please refer to the list below. 

Table 6-37 


Bit 2 

SCR_DIR(Scroll direction) 

ADSR 

Bit 1 

SCR_HV(Scroll Horizontal/Vertical) 

REG[03h] 

Bit 0 

SCR_EN(Scroll Enable) 

BGSG Bit [5:0] The SEG start address in scroll mode REG[61h] 

EDSG Bit [5:0] The SEG end address in scroll mode REG[62h] 

BGCM Bit [7:0] The COM start address in scroll mode REG[71h] 

EDCM Bit [7:0] The COM end address in scroll mode REG[72h] 

(1)Flowchart: The flow-chart of horizontal scrolling is as following: 

Start 

Set Scrolling Window Boundary 

( Set REG[61h],[62h],[71h],[72h]) 

Write Chinese font filled 

with the screen 

Set Scrolling Direction, 

Left to Right 

( Set REG[03h][2:1] = 0 0 ) 

Enable Scrolling Function 

( REG[03h]B0 = 1 ) 

Figure 6-58 : Horizontal Scrolling 


Version 1.3 



(2)Program Example: 

LCD_Text(); 

// Text Mode 

//================================================ 

// Set Scrolling Window 

//================================================ 

LCD_CmdWrite(0x61); // SEG Start Position of Scrolling Mode 

LCD_DataWrite(0x05); 

LCD_CmdWrite(0x62); // SEG End Position of Scrolling Mode 


LCD_CmdWrite(0x71); 



LCD_DataWrite(0xd0); 

// COM Start Position of Scrolling Mode 

// COM End Position of Scrolling Mode 

for( i = 0 ; i < 300 ; i++ ) // Write the font to fill the screen 

{ 

LCD_DataWrite( RAiO [ i ] ); 

Delay2us(50); 

} 

//================================================ 

// Set Scrolling Direction and Enable scroll function 

//================================================ 


LCD_DataWrite(0x01); // L R 

// LCD_DataWrite(0x05); // R L 


Version 1.3 



6-12-2 Vertical Scrolling 

The RA8806 also provide Vertical Scrolling function. You can start the scrolling by control Register 

ADSR Bit-2. Once start the vertical scrolling, the whole screen will shift step by step and each step 

is 1 pixel height. 

(1)Flowchart: The flow-chart of vertical scrolling is as following: 

Start 

Set Scrolling Window Boundary 

( Set REG[61h],[62h],[71h],[72h]) 

Write Chinese font filled 

with the screen 

Set Scrolling Direction, 

Top to Bottom 

( Set REG[03h][2:1] = 0 1 ) 

Enable Scrolling Function 

( REG[03h]B0 = 1 ) 

(2)Program Example: 

Figure 6-59 : Vertical Scrolling 

LCD_Text(); 








LCD_DataWrite(0xd0); 

// Text Mode 

// SEG Start Position of Scrolling Mode 

// SEG End Position of Scrolling Mode 

// COM Start Position of Scrolling Mode 

// COM End Position of Scrolling Mode 

for( i = 0 ; i < 300 ; i++ ) // Fill Chinese font on the screen 

{ 

LCD_DataWrite( RAiO [ i ] ); 

Delay2us(50); 

} 

LCD_CmdWrite(0x03); // Scrolling Enable 

LCD_DataWrite(0x03); // T B 

// LCD_DataWrite(0x07); // B T 


Version 1.3 



6-13 Cursor 

6-13-1 Cursor Position and Shift 

The cursor-moving unit of segment is one byte(or eight pixels). But the moving unit of common is 

one pixel. The cursor position is controlled by Register CURX and CURY for both text and graphics 

mode. You can also setup the Auto-Increase mode for write to DDRAM or read data from DDRAM. 

The cursor-moving boundary depends on the active window. 

6-13-2 Full Alignment 

The “Full alignment function” provides the “Auto-Align” feature when full-size and half-size 

characters combined display. Programmer can adjust it from the settings of Bit-6 of WCCR. (Refer 

to register WCCR for detail description.) 

Appendix A When Bit-6 is 1, the auto-align feature is enabled. 

Appendix B When Bit-6 is 0, the auto-align feature is not being used. 

The Figure 6-60 and Figure 6-61 shows the above settings. 

With full alignment function 

瑞佑科技 

有限公司 

Figure 6-60 : Font Write with Full Alignment 


Version 1.3 



Without full alignment function 

瑞佑科技 

有限公司 

Figure 6-61 : Font Write without Full Alignment 

When the ”Full-alignment” feature is used, the display shows all the full-size characters start from 

the set start address. And there will be an even bytes alignment space between these fonts. For 

half-size character, the function doesn’t restrict the position of it. 

3. Line changing 

and alignment 

setting is reset 

1. Cursor set at 5’th 

bytes 

瑞 

份有限公司 

cursor 

佑科技股 

2. write characters 

CASE 1 

Figure 6-62 : Full-alignment Example(1) 

The full-alignment display rule is base on cursor position be set at 1 st row. After changing row, the 

alignment base is reset. That is, the start segment address of active window. There are serial 

conditions for the changing line with the full alignment feature. Please refer to below figures for the 

condition. 


Version 1.3 




and alignment 


1. Cursor set 

瑞佑科技股 


cursor 

2. Write to the end of the 

line 

CASE 2 



and alignment 


1. Cursor set 

瑞佑科技股 


cursor 

2. No enough space for 

writing a full-size 

character after consider 

full-alignment 

CASE 3 



Version 1.3 



6-13-3 Cursor Blinking 

The user could control cursor On/Off or Blinking. The register [80h] BTMR is used to set up the 

blinking time. 

 

Blinking Time = BTMR[80h] Bit[7:0] x (1/Frame_Rate) 

6-13-4 Cursor Width and Height 

The cursor height is controlled by register CHWI Bit[7:4], and the height is setting from 1 ~ 16 pixel. 

It does depend on user’s requirement. 

In normal font, the cursor width fixed to one byte(8 pixels). And cursor’s height is from 1~16pixels 

that depends on CHWI Bit[7:4]. In vertical font, the cursor height fixed to 16 pixels, and width is 

from 1~8 pixels that depends on CHWI Bit[6:4]. See Figure 6-65 and Figure 6-66 as following. 

瑞佑科技 

Cursor movement for Normal-Font 

Cursor movement for Vertical-Font 

Figure 6-65 : Cursor Movement 

Cursor Size(Height) for Normal-Font 

1 pixel 2 pixel 3 pixel 16 pixel 

Cursor Size(Width) for Vertical-Font 

1 pixel 2 pixel 3 pixel 8 pixel 

Figure 6-66 : Cursor Size 


Version 1.3 



6-14 Extension Mode for Display 

Normally the maximum support resolution of RA8806 is 320x240 dots. But RA8806 support a special 

display mode – Extension mode. And the maximum support resolution is 640x240 or 320x480 dots. In 

Extension mode, the dual DDRAM data can be show on the bigger panel. This mode is set by the Bit[6:4] 

of register MAMR. Please refer to Figure 6-68 of the example by using 640x240 panel, and Figure 6-69 

by using 320x480 panel. 


LCD Driver 

Com/Seg Signals 

LCD Panel 

Max. 320x240 

Normal Mode 

Com/Seg Signals 

LCD Panel 


LCD Driver 

Max. 640x240 

or 

Max. 320x480 

Extension Mod 

Figure 6-67 : Maximum Resolution for RA8806 

320 

320 

240 

DDRAM1 

Data 

DDRAM2 

Data 

Figure 6-68 : Extension Mode(1) Register MAMR Bit[6:4] = 110h 

If MAMR Bit[6:4] = 110b, then RA8806 supports maximum resolution is 640x240 pixels. The left side of 

screen shows the DDRAM1 data, the right side shows the DDRAM2 data. Please refer to Figure 6-68. 

If MAMR Bit[6:4] = 111b, then RA8806 supports maximum resolution is 320x480 pixels. The up side of 

screen shows the DDRAM1 data, the down side shows the DDRAM2 data. Please refer to Figure 6-69. 


Version 1.3 



320 

240 

DDRAM1 

Data 

240 

DDRAM2 

Data 

Figure 6-69 : Extension Mode(2) Register MAMR Bit[6:4] = 111h 

Note that the extension mode is only display the combination of the DDRAM1 and DDRAM2 data. The 

cursor movement or characters display is not continuous across them. So user must set two pages 

separately on the screen. The RA8806 will combine the DDRAM1 and DDRAM2 data as a single display 

in extension mode. So, there is some limitation on Extension Mode. For example, if RA8806 set to 

Extension Mode(1) as Figure 6-68 for 640x240 dots panel. The data have to write into DDRAM1 and 

DDRAM2. But the cursor moving of Common is not from 0 to 639. The users have to separate the 

screen into 2 blocks and write data into DDRAM1 and DDRAM2 to create a complete 640x240 dots 

picture. The Figure 6-70 shows the description. 

: 

: 

: 

: 

: 

: 

: 

: 

: 

: 

DDRAM1 

DDRAM2 

Figure 6-70:Extension Mode(1) Cursor Moving 

Of course, if use Horizontal Scrolling, then the screen is like the following Figure 6-71. 


Version 1.3 



DDRAM1 

DDRAM2 

Figure 6-71:Extension Mode(1) Horizontal Scrolling 

But if RA8806 use Extension mode(2) like Figure 6-69 for 320x480 dots panel, then the cursor moving is 

same as normal mode – the Common is from 0 to 319. The data scan of DDRAM is as Figure 6-72. The 

effect of Horizontal Scrolling is show as Figure 6-73. 

DDRAM1 

: 

: 

: 

: 

: 

DDRAM2 

: 

: 

: 

: 

: 

Figure 6-72:Extension Mode(2) Cursor Moving 

DDRAM1 

DDRAM2 

Figure 6-73:Extension Mode(2) Horizontal Scrolling 


Version 1.3 



6-15 Eliminating Flicker Mode 

RA8806 also provides “Eliminating Flicker Mode” in order to eliminate display errors at scan/MPU 

confliction. When the scan logic is processing scan task and at the same time the DDRAM is accessed 

by the MPU, the scan data will force to get a wrong one and may experience side effects such as 

“flicker”. When the flicker is too much, it will infect the display effect. 

Therefore, RA8806 is designed to disable scan logic when MPU is accessing the DDRAM. And after it is 

completed, the scan logic active again. The “Eliminating Flicker Mode” separate Write and Read 

operating therefore no confliction will happen between scan logic and MPU cycle. That is, no data will 

lose. Ideally, it will have great improvement at display effect. 

In real application, sometimes the cycle time that MPU writes data will be different(font write and 

memory clear), although it accesses the RA8806 periodly. On the other hand, the display performance 

is still limited when operating under the eliminating-flicker mode in some conditions. The limits are : 

(1) The eliminating-flicker mode is suggested to operate under the graphic mode(bit-7 of register[01h] 

is setting 1). 

(2) Please disable eliminating-flicker function before the memory clear mode. After the memory clear 

function is finished, then the eliminating-flicker function could be enable again. 

Figure 6-74 : Eliminating Flicker Mode 

Table 6-38 


MISC Bit 7 The LCD Driver-Scan will auto-pending 

when busy. 

REG[01h] 

Additionly, RA8806 also supply a method to eliminate flicker by check status. By check the status bit- 

6(SCAN BUSY), user can know whether can access memory that doesn’t conflict the scan data period. 

The application figure is below : 


Version 1.3 



Start 

Check status bit-6 

(SCAN BUSY) 

high 

LP 

XCLK 

SCAN_BUSY 

MPU cycle 

low 

Memory access cycle 

ITCR 

: Check status bit-6 = 0 


: Memory access cycle 

Figure 6-75 : Eliminate Flicker (1) Ideal 

LP 

XCLK 

SCAN_BUSY 

MPU cycle 

Confliction! 




Figure 6-76 : Eliminate Flicker (1) Confliction 

The ideal condition just likes the Figure 6-75. But if the condition likes Figure 6-76, the little part of confliction 

that we can not avoid. So if user wants to eliminate the flicker completely by checking SCAN_BUSY, user can 

use the method just like the Figure 6-77. 


Version 1.3 



Start 


(SCAN BUSY) 

high 


(SCAN BUSY) 

low 

Memory access cycle 

low 

high 

LP 

XCLK 

SCAN_BUSY 

MPU cycle 

ITCR 




Figure 6-77 : Eliminate Flicker (2) Ideal 

In order to improve the effect of eliminating flicker by check busy, we have two suggestions in real 

application : 

MPU speed cannot be too slow(The MPU cycle period cannot be too long, just like Figure 6-78), otherwise the 

effect of eliminating flicker will be not eminent. 

The ITCR value cannot be set too small.(just like Figure 6-79), otherwise the effect of eliminating flicker will be 

not eminent. 

So if you want to eliminate flicker by check busy of this way, we support a suggestion ITCR setting value 

just like Figure 6-80 and Figure 6-81. 

LP 

XCLK 

SCAN_BUSY 

MPU cycle 

Confliction! 

ITCR 

MPU cycle too long! 




Figure 6-78 : Eliminate Flicker (2) MPU Cycle Too Long 


Version 1.3 



LP 

XCLK 

SCAN_BUSY 

MPU cycle 

Confliction! 

ITCR 

ITCR period too short 




Figure 6-79 : Eliminate Flicker (2) ITCR Cycle Too Short 

ITCR duration 

SCAN_BUSY 

RD 

Read Status cycle 

Read Status cycle 

MEM write cycle 

ZWR 

MPU 8080 The Worst case!! 

Tcyc 

Tcyc 

tsys = 1/CLK 

CLK : system clock 

M : REG[01h] = 00h M=8 

REG[01h] = 01h M=4 

REG[01h] = 10h M=2 

REG[01h] = 11h M=1 

So ITCR suggestion value is : 

ITCR duration=ITCR x tc x M > 2.5 x Tcyc 

Figure 6-80 : The Suggestion ITCR value for MPU 8080 Interface to Eliminate Flicker 

ITCR duration 

SCAN_BUSY 

RD 

Read Status cycle Read Status cycle MEM write cycle 

ZWR 

MPU 6800 The Worst case!! 

Tcyc 

Tcyc 

tc = 1/CLK 

CLK : system clock 

M : REG[01h] = 00h M=8 

REG[01h] = 01h M=4 

REG[01h] = 10h M=2 

REG[01h] = 11h M=1 

So ITCR suggestion value is : 

ITCR duration=ITCR x tc x M > 2.5 x Tcyc 

Figure 6-81 : The Suggestion ITCR value for MPU 6800 Interface to Eliminate Flicker 


Version 1.3 



7. Package Information 

7-1 Bonding Pad 

CLK_OUT 

TESTMD 

TESTI 

ZRST 

XG 

XD 

DATA7 

DATA6 

DATA5 

DATA4 

DATA3 

DATA2 

DATA1 

DATA0 

ZRD 

ZWR 

VDDP 

GNDP 

RS 

CS2 

RA8806 Logo 

48 

47 

46 

45 

44 

43 

42 

41 

40 

39 

38 

37 

36 

35 

34 

33 

32 

31 

30 

29 

28 

27 

26 

25 

24 

23 

22 

21 

20 

ZCS1 

PWM_OUT 

PWM_OUT 

X1 

Y1 

X2 

Y2 

AVDD 

AGND 


19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

49 

50 

51 

52 

53 

54 

55 

56 

57 

58 

59 

60 

61 

62 

63 

64 

65 

66 

67 

68 

1 

INT 

BUSY 

VDDH 

VDD 

GND 

FR 

LP 

YD 

XCK 

ZDOFF 

LD7 

LD6 

LD5 

LD4 

LD3 

LD2 

LD1 

LD0 

GNDP 

KIN0 

KIN1 

KIN2 

KIN3 

KIN4 

KIN5 

KIN6 

KIN7 

KOUT0 

KOUT1 

KOUT2 

KOUT3 

KOUT4 

KOUT5 

KOUT6 

KOUT7 

DB 

MI 

DW 

VDDP 

Figure 7-1 : RA8806 Bonding Pad 


Version 1.3 



7-2 Pad X/Y Coordinate 

Table 7-1 : RA8806 Pad Coordinate 

Pad No. Pad Name X Y Pad No. Pad Name X Y 

1 GNDP 2301.05 -1649.70 35 DATA0 1429.80 1833.05 

2 LD0 2301.05 -1536.80 36 DATA1 1314.80 1833.05 

3 LD1 2301.05 -1421.80 37 DATA2 1199.80 1833.05 

4 LD2 2301.05 -1306.80 38 DATA3 1084.80 1833.05 

5 LD3 2301.05 -1191.80 39 DATA4 969.80 1833.05 

6 LD4 2301.05 -1076.80 40 DATA5 854.80 1833.05 

7 LD5 2301.05 -961.80 41 DATA6 739.80 1833.05 

8 LD6 2301.05 -846.80 42 DATA7 624.80 1833.05 

9 LD7 2301.05 -731.80 43 XD 509.80 1833.05 

10 ZDOFF 2301.05 -616.80 44 XG 394.80 1833.05 

11 XCK 2301.05 -501.80 45 ZRST 279.80 1833.05 

12 YD 2301.05 -386.80 46 TESTI 164.80 1833.05 

13 LP 2301.05 -271.80 47 TESTMD 49.80 1833.05 

14 FR 2301.05 -156.80 48 CLK_OUT -65.20 1833.05 

15 GND 2301.05 -39.70 49 KIN0 -65.20 -1833.05 

16 VDD 2301.05 75.30 50 KIN1 49.80 -1833.05 

17 VDDH 2301.05 186.10 51 KIN2 164.80 -1833.05 

18 BUSY 2301.05 303.20 52 KIN3 279.80 -1833.05 

19 INT 2301.05 418.20 53 KIN4 394.80 -1833.05 

20 AGND 2301.05 702.20 54 KIN5 509.80 -1833.05 

21 AVDD 2301.05 817.20 55 KIN6 624.80 -1833.05 

22 Y2 2301.05 934.30 56 KIN7 739.80 -1833.05 

23 X2 2301.05 1049.30 57 KOUT0 854.80 -1833.05 

24 Y1 2301.05 1164.30 58 KOUT1 969.80 -1833.05 

25 X1 2301.05 1279.30 59 KOUT2 1084.80 -1833.05 

26 PWM_OUT 2301.05 1394.30 60 KOUT3 1199.80 -1833.05 

27 PWM_OUT 2301.05 1509.30 61 KOUT4 1314.80 -1833.05 

28 ZCS1 2301.05 1624.30 62 KOUT5 1429.80 -1833.05 

29 CS2 2119.80 1833.05 63 KOUT6 1544.80 -1833.05 

30 RS 2004.80 1833.05 64 KOUT7 1659.80 -1833.05 

31 GNDP 1887.70 1833.05 65 DB 1774.80 -1833.05 

32 VDDP 1772.70 1833.05 66 MI 1889.80 -1833.05 

33 ZWR 1659.80 1833.05 67 DW 2004.80 -1833.05 

34 ZRD 1544.80 1833.05 68 VDDP 2121.90 -1833.05 


Version 1.3 



7-3 Pin Assignment 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

CLK_OUT 

NC 

KIN0 

KIN1 

KIN2 

KIN3 

KIN4 

KIN5 

KIN6 

KIN7 

KOUT0 

KOUT1 

KOUT2 

KOUT3 

KOUT4 

KOUT5 

KOUT6 

KOUT7 

DB 

MI 

DW 

80 

85 

90 

95 

100 

75 

70 

TM 


RA8806L2N-T 

Date Code (Year 2008) 

65 

08XX-N 

5 10 15 20 25 30 

60 

55 

50 

45 

40 

35 

TESTMD 

TESTI 

ZRST 

XG 

XD 

NC 

DATA7 

DATA6 

DATA5 

DATA4 

DATA3 

DATA2 

DATA1 

DATA0 

ZRD 

ZWR 

VDDP 

GNDP 

RS 

CS2 

Pin #1 

VDDP 

GNDP 

NC 

NC 

LD0 

LD1 

LD2 

LD3 

LD4 

LD5 

LD6 

LD7 

ZDOFF 

XCK 

YD 

LP 

FR 

GND 

VDD 

VDDH 

BUSY 

INT 

AGND 

AVDD 

Y2 

X2 

Y1 

X1 

PWM_OUT 

ZCS1 

Figure 7-2 : LQFP-100Pin Pin Assignment 

KIN0 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

NC 

CLK_OUT 

KIN1 

KIN2 

KIN3 

KIN4 

KIN5 

KIN6 

KIN7 

KOUT0 

KOUT1 

KOUT2 

KOUT3 

KOUT4 

KOUT5 

KOUT6 

KOUT7 

DB 

MI 

VDDP 

GNDP 

LD0 

60 

65 

70 

75 

80 

55 

50 

45 40 TESTMD 

TESTI 

ZRST 

XG 

TM 

XD 

35 DATA7 

DATA6 

DATA5 

DATA4 

DATA3 

30 DATA2 

DATA1 

DATA0 

ZRD 

08XX-N 

ZWR 

25 VDDP 

Date Code(Year 2008) 

GNDP 

RS 

CS2 

5 10 15 20 

ZCS1 


RA8806T1N-S 

Pin #1 

LD1 

LD2 

LD3 

ZDOFF 

XCK 

YD 

LP 

FR 

GND 

VDD 

VDDH 

BUSY 

INT 

AGND 

AVDD 

Y2 

X2 

Y1 

X1 

PWM_OUT 

Figure 7-3 : TQFP-80Pin Pin Assignment 


Version 1.3 



7-4 Package Dimension 

Pin-1 Index 

b 

08xx-N 

RA8806L2N-S/T 

RAiO TM 

D1 

D 

e 

E1 

E 

Seating Plane 

0.10mm 

Detail A 

θ2 

θ1 

C 

A2 

A 

R1 

R2 

0.25mm 

Gauge Plane 

A1 

θ3 

L 

θ 

L1 

Detail A 

Figure 7-4 : LQFP-100Pin Mechanical 


Version 1.3 



Table 7-2 : LQFP-100 Package Dimension 

Symbols 

Dimensions in Millimeters 

Dimensions in Inches 

Min. Typ. Max. Min. Typ. Max. 

A -- -- 1.60 -- -- 0.063 

A1 0.05 -- 0.15 0.002 -- 0.006 

A2 1.35 1.40 1.45 0.053 0.055 0.057 

b 0.22 0.3 0.33 0.009 0.012 0.013 

c 0.09 -- 0.16 0.004 -- 0.006 

e 0.65 BSC. 0.026 BSC. 

D 22.00 BSC. 0.866 BSC. 

D1 20.00 BSC. 0.787 BSC. 

E 16.00 BSC. 0.630 BSC. 

E1 14.00 BSC. 0.551 BSC. 

L 0.45 0.60 0.75 0.018 0.024 0.030 

L1 1.00 Ref. 0.039 Ref. 

R1 0.08 -- -- 0.003 -- -- 

R2 0.08 -- 0.20 0.003 -- 0.008 

θ 0 3.5° 7° 0 3.5° 7° 

θ1 0 -- -- 0 -- -- 

θ2 11° 12° 13° 11° 12° 13° 

θ3 11° 12° 13° 11° 12° 13° 

Note: 

Dimension “D1” and “E1” do not include mold protrusion. Allowable protrusion is 0.25mm per side. 

“D1” and “E1” are maximum plastic body size dimensions including mold mismatch. 


Version 1.3 



Figure 7-5 : TQFP-80Pin Mechanical 


Version 1.3 



Table 7-3 : TQFP-80 Package Dimension 

Symbols 

Dimensions in Millimeters 

Dimensions in Inches 

Min. Typ. Max. Min. Typ. Max. 

A -- -- 1.20 -- -- 0.047 

A1 0.05 0.10 0.15 0.002 0.004 0.006 

A2 0.95 1.00 1.05 0.037 0.039 0.041 

b 0.13 0.18 0.23 0.005 0.007 0.009 

b1 0.13 0.16 0.19 0.005 0.006 0.007 

c 0.09 -- 0.20 0.004 -- 0.008 

c1 0.09 0.127 0.16 0.004 0.005 0.006 

e 0.40 BSC. 0.016 BSC. 

D 11.90 12.00 12.10 0.469 0.472 0.476 

D1 9.90 10.00 10.10 0.390 0.394 0.398 

E 11.90 12.00 12.10 0.469 0.472 0.476 

E1 9.90 10.00 10.10 0.390 0.394 0.398 

L 0.45 0.60 0.75 0.018 0.024 0.030 

L1 1.00 Ref. 0.040 Ref. 

R1 0.08 -- -- 0.003 -- -- 

R2 0.08 -- 0.20 0.003 -- 0.008 

θ 0 3° 7° 0 3° 7° 


Version 1.3 



7-5 Part Number 

Product Name 

(Full Name) 

RA8806L2N-T 

RA8806L2N-S 

RA8806L2N-J 

RA8806T1N-T 

RA8806T1N-S 

RA8806T1N-J 

Resolution 

(Max) 

320x240 

(Note 1) 

Table 7-4 : Part Number 

Package Font ROM ASCII ROM 

RoHs 

Compliance 

Traditional Chinese 

(Note 2) 

ISO-8859-1 ~ 4 Yes 

LQFP-100 

Simple Chinese 

(20x14) (Note 2) 

ISO-8859-1 ~ 4 Yes 

Japanese Kanji ISO-8859-1 ~ 4 Yes 

Traditional Chinese 

(Note 2, 3) 

ISO-8859-1 ~ 4 Yes 

TQFP-80 Simple Chinese 

(10x10) 

(Note 2, 3) 

ISO-8859-1 ~ 4 Yes 

(Note 3) 

Japanese Kanji 

ISO-8859-1 ~ 4 Yes 

RA8806-T Traditional Chinese ISO-8859-1 ~ 4 Yes 

Die 

RA8806-S 

Simple Chinese ISO-8859-1 ~ 4 Yes 

Notes: 

1. In Extension Mode, the maximum resolution is 640x240 or 320x480. See Section 6-14 “Extension 

Mode and Display”. 

2. In both Traditional and Simple Chinese font, it built-in 52 basic Japanese font. 

3. LCD driver data bus of RA8806T1N is 4-bits. 

4. All of the parts of RA008 are RoHS compliance and pass the detection of free PFOS and PFOA. 

Table 7-5 : RA8806L2N vs. RA8806T1N 

Difference RA8806L2N RA8806T1N 

LQFP-100Pins TQFP-80Pins 

Package 

20mm x 14mm 10mm x 10mm 

LCD Data Bus 4-bits or 8-bits 4-bits 


Version 1.3 



8. Electrical Characteristic 

8-1 Absolute Maximum Ratings 

Table 8-1 : Absolute Maximum Ratings 

Parameter Symbol Rating Unit 

Supply Voltage Range V DD -0.3 to 6.5 V 

Input Voltage Range V IN -0.3 to V DD +0.3 V 

Power Dissipation (VDD = 5V) P D ≦30 mW 

Operation Temperature Range T OPR -30 to +85 ℃ 

Storage Temperature T ST -45 to +125 ℃ 

Soldering temperature (10 

seconds). See Note 1. 

T SOLDER 260 ℃ 

Notes: 

1. The humidity resistance of the flat package may be reduced if the package is immersed in 

solder. Use a soldering technique that does not heat stress the package. 

2. If the power supply has a high impedance, a large voltage differential can occur between the 

input and supply voltages. Take appropriate care with the power supply and the layout of the 

supply lines. 

3. All supply voltages are referenced to Gnd = 0V. 


Version 1.3 



8-2 DC Characteristic 

Table 8-2 : DC Characteristic 

Parameter Symbol Min. Typ. Max. Unit Condition 

Operating Voltage(1) V DDP / V DDH 4.5 5.0 5.5 V 

V DDP = V DDH 

(Refer to 

Figure 6-31) 

Operating Voltage(2) V DDP / V DD 2.4 3.3 3.6 V 

V DDP = V DD 

V DDH Open 

(Refer to 

Figure 6-30) 

Oscillator frequency F OSC 4 8 12 MHz V DD = 5V 

External clock frequency F CLK 4 8 12 MHz V DD = 5V 

DC to DC Output Voltage V DD 2.8V 3.0 3.3 V 

Input 

Add external 

1uF Capacitor 

Input High Voltage V IH 0.8xV DD -- V DD V See Note 1, 3 

Input Low Voltage V IL Gnd -- 0.2xV DD V See Note 1, 3 

Output 

Output High Voltage V IH V DD -0.4 -- V DD V See Note 2, 3 

Output Low Voltage V IL Gnd -- Gnd+0.4 V See Note 2, 3 

Schmitt-trigger 

Input High Voltage V IH 0.7xV DD 

-- -- V See Note 4 

Input Low Voltage V IL -- -- 0.25xV DD V See Note 4 

Input Leakage Current 1 I IH -- -- +1 μA 

Input Leakage Current 2 I IL -- -- -1 μA 

Operation Current I OPR 1 5 10 mA 

Standby Mode Current 

(Normal Mode Current) 

Display Off Current 

Sleep Mode 

I SB 

I DISPLAY 

I SLP 

-- 1.5 1.8 mA Case1 

1.8 2.1 mA Case2 

-- 120 140 μA Case1 

140 160 μA Case2 

-- 0.5 1 μA Case1 

-- 20 25 μA Case2 

Notes: 

1. ZCS1, CS2, ZWR, ZRD, RS, MI, DW, DB, KIN[7:0], TESTMD and TESTI are inputs. KIN[7:0] 

built-in pull up resistors. The TESTMD and TESTI built-in pull down resistors. 

2. INT, BUSY, CLK_OUT, PWM_OUT, KOUT[7:0], LP, FR, YD, ZDOFF, XCK and LD[7:0] are 

outputs. 

3. DATA[7:0] are Bi-direction. 

4. The ZRST are Schmitt-trigger with pull-up input. The pulse width on ZRST must be at least 

1024*tc. Note that pulses of more than a few seconds will cause DC voltages to be applied to 

the LCD panel. 

Case1: V DDP = V DD = A VDD = 3.3V, V DDH = NC, LCD Driver VDD = 5V, CLK = 4MHz, CLK_OUT: 

Off, Segment=160, Common=160, FRM = 78Hz, T A =25 ℃ . 

Case2: V DDP = V DDH = 5V, V DD = A VDD = 3V, LCD Driver VDD = 3.3V, CLK = 4MHz, CLK_OUT: 

Off, Segment=160, Common=160, FRM = 78Hz, T A =25 ℃ . 


Version 1.3 



8-3 Timing Characteristic Wavaform 

Figure 8-1 is timing characteristic waveform and parameters for RA8806 driver interface signal. 

tWLPH 

tLH 

LP 

XCK 

tSL 

tLS 

tWCKH 

tWCKH 

tWCKL 

tLD 

tWCK 

XD[7:0] LAST DATA TOP DATA 

tDS 

tDH 

ITCR 

Figure 8-1 : Timing Characteristic Waveform 

Table 8-3: Parameters 

Parameter 

Symbol 

condition 

Min. 

Typ. 

Max. 

Unit 

Note 

Shift Clock period 

t WCK 

Tsys/D 

ns 

*1 

Shift Clock “H” Pulse Width 

t WCKH 

t WCK /2 -10 

t WCK /2 +10 

ns 

Shift Clock “L” Pulse Width 

t WCKL 

t WCK /2 -10 

t WCK /2 +10 

ns 

Data Setup Time 

t DS 

t WCK /2 -30 

t WCK /2 

ns 

Data Hold Time 

t DH 

t WCK /2 

t WCK /2 +30 

ns 

Latch Pulse “H” Pulse Width 

t WLPH 

t WCK -10 

t WCK +10 

ns 

Shift Clock Rise to Latch 

Pulse Rise Time 

t LD 

0 

ns 

Shift Clock Fall to Latch 

Pulse Fall Time 

t SL 

t WCK /2 -10 

t WCK /2 +10 

ns 

Latch Clock Rise to Shift 


t LS 

t WCK /2 -10 

ns 

*2 

Latch Clock Rise to Shift 


t LH 

t WCK /2 -10 

ns 

*2 

Note : 

1. Tsys : system clock period(i.e. System clock = 12MHz, Tsys = 83.3ns) 

D : Driver clock selection(REG[01h] B3-2) 

0 0 : XCK = CLK/8 

0 1 : XCK = CLK/4(initial value) 

1 0 : XCK = CLK/2 

1 1 : XCK = CLK 

2.The period also depends on the setting of register ITCR. 


Version 1.3 



Appendix A . Application Circuit 

Figure A-1 : Application Circuit for 3V or 5V 


Version 1.3 



Appendix B . Frame Rate Table 

Seg 

Com 

CLK 

(MHz) 

Table B-1 : Frame Rate Table(1) 

XCK=CLK/2 

REG[01h] Bit[3:2] = 10 

Frame Rate REG[90h] 

(Hz) 

ITCR 

XCK=CLK/4 

REG[01h] Bit[3:2] = 01 


(Hz) 

ITCR 

XCK=CLK/8 

REG[01h] Bit[3:2] = 00 


(Hz) ITCR 

320 240 4 55 72 55 -- 55 -- 

320 240 4 60 59 60 -- 60 -- 

320 240 4 65 48 65 -- 65 -- 

320 240 4 70 39 70 -- 70 -- 

320 240 4 75 31 75 -- 75 -- 

320 240 6 55 147 55 34 55 -- 

320 240 6 60 128 60 24 60 -- 

320 240 6 65 112 65 16 65 -- 

320 240 6 70 99 70 9 70 -- 

320 240 6 75 87 75 3 75 -- 

320 240 8 55 223 55 72 55 -- 

320 240 8 60 198 60 59 60 -- 

320 240 8 65 176 65 48 65 -- 

320 240 8 70 158 70 39 70 -- 

320 240 8 75 142 75 31 75 -- 

320 240 10 55 -- 55 109 55 15 

320 240 10 60 -- 60 94 60 7 

320 240 10 65 241 65 80 65 -- 

320 240 10 70 218 70 69 70 -- 

320 240 10 75 198 75 59 75 -- 

320 240 12 55 -- 55 147 55 34 

320 240 12 60 -- 60 128 60 24 

320 240 12 65 -- 65 112 65 16 

320 240 12 70 -- 70 99 70 9 

320 240 12 75 253 75 87 75 3 

240 160 4 55 167 55 54 55 -- 

240 160 4 60 148 60 44 60 -- 

240 160 4 65 132 65 36 65 -- 

240 160 4 70 119 70 29 70 -- 

240 160 4 75 107 75 23 75 -- 

240 160 6 55 -- 55 110 55 25 

240 160 6 60 -- 60 96 60 18 

240 160 6 65 228 65 84 65 12 

240 160 6 70 208 70 74 70 7 

240 160 6 75 190 75 65 75 3 

240 160 8 55 -- 55 167 55 54 

240 160 8 60 -- 60 148 60 44 

240 160 8 65 -- 65 132 65 36 

240 160 8 70 -- 70 119 70 29 

240 160 8 75 -- 75 107 75 23 

240 160 10 55 -- 55 224 55 82 

240 160 10 60 -- 60 200 60 70 

240 160 10 65 -- 65 180 65 60 

240 160 10 70 -- 70 163 70 52 

240 160 10 75 -- 75 148 75 44 

240 160 12 55 -- 55 -- 55 110 

240 160 12 60 -- 60 253 60 96 

240 160 12 65 -- 65 228 65 84 

240 160 12 70 -- 70 208 70 74 

240 160 12 75 -- 75 190 75 65 


Version 1.3 



Seg 

Com 

CLK 

(MHz) 


XCK=CLK/2 

REG[01h] Bit[3:2] = 10 

Frame Rate 

(Hz) 

REG[90h] 

ITCR 

XCK=CLK/4 

REG[01h] Bit[3:2] = 01 

Frame Rate 

(Hz) 

ITCR 

XCK=CLK/8 

REG[01h] Bit[3:2] = 00 

Frame Rate 

(Hz) 

REG[90h] 

ITCR 

160 160 4 55 187 55 74 55 17 

160 160 4 60 168 60 64 60 12 

160 160 4 65 152 65 56 65 8 

160 160 4 70 139 70 49 70 5 

160 160 4 75 127 75 43 75 2 

160 160 6 55 -- 55 130 55 45 

160 160 6 60 -- 60 116 60 38 

160 160 6 65 248 65 104 65 32 

160 160 6 70 228 70 94 70 27 

160 160 6 75 210 75 85 75 23 

160 160 8 55 -- 55 187 55 74 

160 160 8 60 -- 60 168 60 64 

160 160 8 65 -- 65 152 65 56 

160 160 8 70 -- 70 139 70 49 

160 160 8 75 -- 75 127 75 43 

160 160 10 55 -- 55 244 55 102 

160 160 10 60 -- 60 220 60 90 

160 160 10 65 -- 65 200 65 80 

160 160 10 70 -- 70 183 70 72 

160 160 10 75 -- 75 168 75 64 

160 160 12 55 -- 55 -- 55 130 

160 160 12 60 -- 60 -- 60 116 

160 160 12 65 -- 65 248 65 104 

160 160 12 70 -- 70 228 70 94 

160 160 12 75 -- 75 210 75 85 

160 128 4 55 244 55 102 55 31 

160 128 4 60 220 60 90 60 25 

160 128 4 65 200 65 80 65 20 

160 128 4 70 183 70 72 70 16 

160 128 4 75 168 75 64 75 12 

160 128 6 55 -- 55 173 55 67 

160 128 6 60 -- 60 155 60 58 

160 128 6 65 -- 65 140 65 50 

160 128 6 70 -- 70 127 70 44 

160 128 6 75 -- 75 116 75 38 

160 128 8 55 -- 55 244 55 102 

160 128 8 60 -- 60 220 60 90 

160 128 8 65 -- 65 200 65 80 

160 128 8 70 -- 70 183 70 72 

160 128 8 75 -- 75 168 75 64 

160 128 10 55 -- 55 -- 55 138 

160 128 10 60 -- 60 -- 60 123 

160 128 10 65 -- 65 -- 65 110 

160 128 10 70 -- 70 239 70 100 

160 128 10 75 -- 75 220 75 90 

160 128 12 55 -- 55 -- 55 173 

160 128 12 60 -- 60 -- 60 155 

160 128 12 65 -- 65 -- 65 140 

160 128 12 70 -- 70 -- 70 127 

160 128 12 75 -- 75 -- 75 116 


Version 1.3 



Seg 

Com 

CLK 

(MHz) 


XCK=CLK/2 

REG[01h] Bit[3:2] = 10 

Frame Rate 

(Hz) 

REG[90h] 

ITCR 

XCK=CLK/4 

REG[01h] Bit[3:2] = 01 

Frame Rate 

(Hz) 

REG[90h] 

ITCR 

XCK=CLK/8 

REG[01h] Bit[3:2] = 00 

Frame Rate 

(Hz) 

REG[90h] 

ITCR 

240 128 4 55 224 55 82 55 11 

240 128 4 60 200 60 70 60 5 

240 128 4 65 180 65 60 65 -- 

240 128 4 70 163 70 52 70 -- 

240 128 4 75 148 75 44 75 -- 

240 128 6 55 -- 55 153 55 47 

240 128 6 60 -- 60 135 60 38 

240 128 6 65 -- 65 120 65 30 

240 128 6 70 -- 70 107 70 24 

240 128 6 75 253 75 96 75 18 

240 128 8 55 -- 55 224 55 82 

240 128 8 60 -- 60 200 60 70 

240 128 8 65 -- 65 180 65 60 

240 128 8 70 -- 70 163 70 52 

240 128 8 75 -- 75 148 75 44 

240 128 10 55 -- 55 -- 55 118 

240 128 10 60 -- 60 -- 60 103 

240 128 10 65 -- 65 240 65 90 

240 128 10 70 -- 70 219 70 80 

240 128 10 75 -- 75 200 75 70 

240 128 12 55 -- 55 -- 55 153 

240 128 12 60 -- 60 -- 60 135 

240 128 12 65 -- 65 -- 65 120 

240 128 12 70 -- 70 -- 70 107 

240 128 12 75 -- 75 253 75 96 

240 64 4 55 -- 55 224 55 82 

240 64 4 60 -- 60 200 60 70 

240 64 4 65 -- 65 180 65 60 

240 64 4 70 -- 70 163 70 52 

240 64 4 75 -- 75 148 75 44 

240 64 6 55 -- 55 -- 55 153 

240 64 6 60 -- 60 -- 60 135 

240 64 6 65 -- 65 -- 65 120 

240 64 6 70 -- 70 -- 70 107 

240 64 6 75 -- 75 253 75 96 

240 64 8 55 -- 55 -- 55 224 

240 64 8 60 -- 60 -- 60 200 

240 64 8 65 -- 65 -- 65 180 

240 64 8 70 -- 70 -- 70 163 

240 64 8 75 -- 75 -- 75 148 

240 64 10 55 -- 55 -- 55 -- 

240 64 10 60 -- 60 -- 60 -- 

240 64 10 65 -- 65 -- 65 240 

240 64 10 70 -- 70 -- 70 219 

240 64 10 75 -- 75 -- 75 200 

240 64 12 55 -- 55 -- 55 -- 

240 64 12 60 -- 60 -- 60 -- 

240 64 12 65 -- 65 -- 65 -- 

240 64 12 70 -- 70 -- 70 -- 

240 64 12 75 -- 75 -- 75 253 

Note: The value of ITCR is in decimal. 


Version 1.3 



Appendix C . Font Table - ASCII 

When Bit-7 of register “FNCR” is “0”, the contents of ASCII Block Tables 1-4 are show as following Table C- 

1~ Table C-3. 

Table C-1 : ASCII Block 1 

H L 

0 1 2 3 4 5 6 7 8 9 A B C D E F 

0 

1 

2 

3 

4 

5 

6 

7 

8 

9 

A 

B 

C 

D 

E 

F 


Version 1.3 




H L 

0 1 2 3 4 5 6 7 8 9 A B C D E F 

0 

1 

2 

3 

4 

5 

6 

7 

8 

9 

A 

B 

C 

D 

E 

F 


Version 1.3 




H L 

0 1 2 3 4 5 6 7 8 9 A B C D E F 

0 

1 

2 

3 

4 

5 

6 

7 

8 

9 

A 

B 

C 

D 

E 

F 


Version 1.3 




H L 

0 1 2 3 4 5 6 7 8 9 A B C D E F 

0 

1 

2 

3 

4 

5 

6 

7 

8 

9 

A 

B 

C 

D 

E 

F 


Version 1.3 



When Bit-7 of register “FNCR” is “1”, the contents of ASCII Block Tables 1-4 are show as following Table C- 

5 ~ Table C-8. 

Table C-5 shows the standard character encoding of ISO/IEC 8859-1. ISO means International 

Organization for Standardization. The ISO 8859-1 also less formally called “Latin-1” is he first eight-bits 

coded character sets that developed by the ISO. It refers to ASCII that consisting of 192 characters from the 

Latin script in range 0xA0-0xFF. This character encoding is used throughout Western Europe, includes 

Albanian, Afrikaans, Breton, Danish, Faroese, Frisian, Galician, German, Greenlandic, Icelandic, Irish, 

Italian, Latin, Luxembourgish, Norwegian, Portuguese, Rhaeto-Romanic, Scottish Gaelic, Spanish, Swedish. 

English letters with no accent marks also can use ISO 8859-1. 

In addition, it also commonly used in many languages outside Europe, such as Swahili, Indonesian, 

Malaysian and Tagalog. 

Table C-5 : ASCII Block 1(ISO 8859-1) 


Version 1.3 



Table C-6 shows the standard characters of ISO/IEC 8859-2. ISO 8859-2 also cited as Latin-2 is the part 2 

of the eight-bits coded character sets developed by ISO/IEC 8859. These code values can be used in 

almost any data interchange system to communicate in the following European languages : Croatian, Czech, 

Hungarian, Polish, Slovak, Slovenian, and Upper Sorbian. The Serbian, English, German, Latin can use 

ISO 8859-2 as well. Furthermore it is suitable to represent some western European languages like Finnish 

(with the exception of å used in Swedish and Finnish) 



Version 1.3 



Table C-7 shows the standard characters of ISO/IEC 8859-3. ISO 8859-3 also known as Latin-3 or “South 

European” is an eight-bits character encoding, third part of the ISO 8859 standard. It was designed 

originally to cover Turkish, Maltese and Esperanto, though the introduction of ISO 8859-9 superseded it for 

Turkish. The encoding remains popular with users of Esperanto and Maltese, though it also supports 

English, German, Italian, Latin and Portuguese. 



Version 1.3 



Table C-8 shows the standard characters of ISO/IEC 8859-4. ISO 8859-4 is known as Latin-4 or “ North 

European”,is the forth part of the ISO 8859 eight-bits character encoding. It was designed originally to 

cover Estonian, Greenlandic, Latvian, Lithuanian, and Sami. This character set also supports Danish, 

English, Finnish, German, Latin, Norwegian, Slovenian, and Swedish. 



Version 1.3 



Appendix D . Font Table - GB Code 


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Appendix E . Font Table - BIG-5 Code 

A1 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 , 、。 . ‧ ; : ? ! .. … ‥ , 、 . 

5 · ; : ? ! | – — — _ ╴ _ ﹏ ( ) ( 

6 ) { } { } [ ] 〔〕【】【】《》《 

7 》〈〉 ^ 〉「」「」『』『』 ( ) 

A { } 〔〕 ‘ ’ “ ” 〝〞 ‵ ′ # & * 

B ※ § 〃 ○ ● △ ▲ ◎ ☆ ★ ◇ ◆ □ ■ ▽ ▼ 

C 正 ℅ ¯ ̄ _ ˍ ﹉﹊﹍﹎﹋﹌ # & * + 

D - × ÷ ± √ < > = ≦ ≧ ≠ ∞ ≒ ≡ + - 

E < > = ~ ∩ ∪ ⊥ ∠ ∟ ⊿ log ln ∫ ∮ ∵ ∴ 

F ♀ ♂ ♁ ☉ ↑ ↓ ← → ↖ ↗ ↙ ↘ ∥ ∣ / 

A2 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 \ ⁄ \ $ ¥ 〒 ¢ £ % @ ℃ ℉ $ % @ mil 

5 mm cm km KM m2 mg kg cc ° 兙兛兞兝兡兣嗧 

6 瓩糎 ▁ ▂ ▃ ▄ ▅ ▆ ▇ █ ▏ ▎ ▍ ▌ ▋ ▊ 

7 ▉ ┼ ┴ ┬ ┤ ├ ▔ ─ │ ▕ ┌ ┐ └ ┘ ╭ 

A ╮ ╰ ╯ ═ ╞ ╪ ╡ ◢ ◣ ◥ ◤ ╱ ╲ ╳ 0 

B 1 2 3 4 5 6 7 8 9 Ⅰ Ⅱ Ⅲ Ⅳ Ⅴ Ⅵ Ⅶ 

C Ⅷ Ⅸ Ⅹ 〡〢〣〤〥〦〧〨〩十卄卅 A 

D B C D E F G H I J K L M N O P Q 

E R S T U V W X Y Z a b c d e f g 

F h i j k l m n o p q r s t u v 

A3 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 w x y z Α Β Γ Δ Ε Ζ Η Θ Ι Κ Λ Μ 

5 Ν Ξ Ο Π Ρ Σ Τ Υ Φ Χ Ψ Ω α β γ δ 

6 ε ζ η θ ι κ λ μ ν ξ ο π ρ σ τ υ 

7 φ χ ψ ω ㄅㄆㄇㄈㄉㄊㄋㄌㄍㄎㄏ 

A ㄐㄑㄒㄓㄔㄕㄖㄗㄘㄙㄚㄛㄜㄝㄞ 

B ㄟㄠㄡㄢㄣㄤㄥㄦㄧㄨㄩ ․ ˊ ˇ ˋ 

C 

D 

E € 

F 


Version 1.3 



A4 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 一乙丁七乃九了二人儿入八几刀刁力 

5 匕十卜又三下丈上丫丸凡久么也乞于 

6 亡兀刃勺千叉口土士夕大女子孑孓寸 

7 小尢尸山川工己已巳巾干廾弋弓才 

A 丑丐不中丰丹之尹予云井互五亢仁 

B 什仃仆仇仍今介仄元允內六兮公冗凶 

C 分切刈勻勾勿化匹午升卅卞厄友及反 

D 壬天夫太夭孔少尤尺屯巴幻廿弔引心 

E 戈戶手扎支文斗斤方日曰月木欠止歹 

F 毋比毛氏水火爪父爻片牙牛犬王丙 

A5 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 世丕且丘主乍乏乎以付仔仕他仗代令 

5 仙仞充兄冉冊冬凹出凸刊加功包匆北 

6 匝仟半卉卡占卯卮去可古右召叮叩叨 

7 叼司叵叫另只史叱台句叭叻四囚外 

A 央失奴奶孕它尼巨巧左市布平幼弁 

B 弘弗必戊打扔扒扑斥旦朮本未末札正 

C 母民氐永汁汀氾犯玄玉瓜瓦甘生用甩 

D 田由甲申疋白皮皿目矛矢石示禾穴立 

E 丞丟乒乓乩亙交亦亥仿伉伙伊伕伍伐 

F 休伏仲件任仰仳份企伋光兇兆先全 

A6 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 共再冰列刑划刎刖劣匈匡匠印危吉吏 

5 同吊吐吁吋各向名合吃后吆吒因回囝 

6 圳地在圭圬圯圩夙多夷夸妄奸妃好她 

7 如妁字存宇守宅安寺尖屹州帆并年 

A 式弛忙忖戎戌戍成扣扛托收早旨旬 

B 旭曲曳有朽朴朱朵次此死氖汝汗汙江 

C 池汐汕污汛汍汎灰牟牝百竹米糸缶羊 

D 羽老考而耒耳聿肉肋肌臣自至臼舌舛 

E 舟艮色艾虫血行衣西阡串亨位住佇佗 

F 佞伴佛何估佐佑伽伺伸佃佔似但佣 

Example: The BIG-5 code of “ 中 ” is A4, A4, and BIG-5 code of “ 世 ” is A5, 40. 


Version 1.3 



A7 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 作你伯低伶余佝佈佚兌克免兵冶冷別 

5 判利刪刨劫助努劬匣即卵吝吭吞吾否 

6 呎吧呆呃吳呈呂君吩告吹吻吸吮吵吶 

7 吠吼呀吱含吟听囪困囤囫坊坑址坍 

A 均坎圾坐坏圻壯夾妝妒妨妞妣妙妖 

B 妍妤妓妊妥孝孜孚孛完宋宏尬局屁尿 

C 尾岐岑岔岌巫希序庇床廷弄弟彤形彷 

D 役忘忌志忍忱快忸忪戒我抄抗抖技扶 

E 抉扭把扼找批扳抒扯折扮投抓抑抆改 

F 攻攸旱更束李杏材村杜杖杞杉杆杠 

A8 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 杓杗步每求汞沙沁沈沉沅沛汪決沐汰 

5 沌汨沖沒汽沃汲汾汴沆汶沍沔沘沂灶 

6 灼災灸牢牡牠狄狂玖甬甫男甸皂盯矣 

7 私秀禿究系罕肖肓肝肘肛肚育良芒 

A 芋芍見角言谷豆豕貝赤走足身車辛 

B 辰迂迆迅迄巡邑邢邪邦那酉釆里防阮 

C 阱阪阬並乖乳事些亞享京佯依侍佳使 

D 佬供例來侃佰併侈佩佻侖佾侏侑佺兔 

E 兒兕兩具其典冽函刻券刷刺到刮制剁 

F 劾劻卒協卓卑卦卷卸卹取叔受味呵 

A9 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 咖呸咕咀呻呷咄咒咆呼咐呱呶和咚呢 

5 周咋命咎固垃坷坪坩坡坦坤坼夜奉奇 

6 奈奄奔妾妻委妹妮姑姆姐姍始姓姊妯 

7 妳姒姅孟孤季宗定官宜宙宛尚屈居 

A 屆岷岡岸岩岫岱岳帘帚帖帕帛帑幸 

B 庚店府底庖延弦弧弩往征彿彼忝忠忽 

C 念忿怏怔怯怵怖怪怕怡性怩怫怛或戕 

D 房戾所承拉拌拄抿拂抹拒招披拓拔拋 

E 拈抨抽押拐拙拇拍抵拚抱拘拖拗拆抬 

F 拎放斧於旺昔易昌昆昂明昀昏昕昊 


Version 1.3 



AA 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 昇服朋杭枋枕東果杳杷枇枝林杯杰板 

5 枉松析杵枚枓杼杪杲欣武歧歿氓氛泣 

6 注泳沱泌泥河沽沾沼波沫法泓沸泄油 

7 況沮泗泅泱沿治泡泛泊沬泯泜泖泠 

A 炕炎炒炊炙爬爭爸版牧物狀狎狙狗 

B 狐玩玨玟玫玥甽疝疙疚的盂盲直知矽 

C 社祀祁秉秈空穹竺糾罔羌羋者肺肥肢 

D 肱股肫肩肴肪肯臥臾舍芳芝芙芭芽芟 

E 芹花芬芥芯芸芣芰芾芷虎虱初表軋迎 

F 返近邵邸邱邶采金長門阜陀阿阻附 

AB 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 陂隹雨青非亟亭亮信侵侯便俠俑俏保 

5 促侶俘俟俊俗侮俐俄係俚俎俞侷兗冒 

6 冑冠剎剃削前剌剋則勇勉勃勁匍南卻 

7 厚叛咬哀咨哎哉咸咦咳哇哂咽咪品 

A 哄哈咯咫咱咻咩咧咿囿垂型垠垣垢 

B 城垮垓奕契奏奎奐姜姘姿姣姨娃姥姪 

C 姚姦威姻孩宣宦室客宥封屎屏屍屋峙 

D 峒巷帝帥帟幽庠度建弈弭彥很待徊律 

E 徇後徉怒思怠急怎怨恍恰恨恢恆恃恬 

F 恫恪恤扁拜挖按拼拭持拮拽指拱拷 

AC 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 拯括拾拴挑挂政故斫施既春昭映昧是 

5 星昨昱昤曷柿染柱柔某柬架枯柵柩柯 

6 柄柑枴柚查枸柏柞柳枰柙柢柝柒歪殃 

7 殆段毒毗氟泉洋洲洪流津洌洱洞洗 

A 活洽派洶洛泵洹洧洸洩洮洵洎洫炫 

B 為炳炬炯炭炸炮炤爰牲牯牴狩狠狡玷 

C 珊玻玲珍珀玳甚甭畏界畎畋疫疤疥疢 

D 疣癸皆皇皈盈盆盃盅省盹相眉看盾盼 

E 眇矜砂研砌砍祆祉祈祇禹禺科秒秋穿 

F 突竿竽籽紂紅紀紉紇約紆缸美羿耄 


Version 1.3 



AD 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 耐耍耑耶胖胥胚胃胄背胡胛胎胞胤胝 

5 致舢苧范茅苣苛苦茄若茂茉苒苗英茁 

6 苜苔苑苞苓苟苯茆虐虹虻虺衍衫要觔 

7 計訂訃貞負赴赳趴軍軌述迦迢迪迥 

A 迭迫迤迨郊郎郁郃酋酊重閂限陋陌 

B 降面革韋韭音頁風飛食首香乘亳倌倍 

C 倣俯倦倥俸倩倖倆值借倚倒們俺倀倔 

D 倨俱倡個候倘俳修倭倪俾倫倉兼冤冥 

E 冢凍凌准凋剖剜剔剛剝匪卿原厝叟哨 

F 唐唁唷哼哥哲唆哺唔哩哭員唉哮哪 

AE 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 哦唧唇哽唏圃圄埂埔埋埃堉夏套奘奚 

5 娑娘娜娟娛娓姬娠娣娩娥娌娉孫屘宰 

6 害家宴宮宵容宸射屑展屐峭峽峻峪峨 

7 峰島崁峴差席師庫庭座弱徒徑徐恙 

A 恣恥恐恕恭恩息悄悟悚悍悔悌悅悖 

B 扇拳挈拿捎挾振捕捂捆捏捉挺捐挽挪 

C 挫挨捍捌效敉料旁旅時晉晏晃晒晌晅 

D 晁書朔朕朗校核案框桓根桂桔栩梳栗 

E 桌桑栽柴桐桀格桃株桅栓栘桁殊殉殷 

F 氣氧氨氦氤泰浪涕消涇浦浸海浙涓 

AF 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 浬涉浮浚浴浩涌涊浹涅浥涔烊烘烤烙 

5 烈烏爹特狼狹狽狸狷玆班琉珮珠珪珞 

6 畔畝畜畚留疾病症疲疳疽疼疹痂疸皋 

7 皰益盍盎眩真眠眨矩砰砧砸砝破砷 

A 砥砭砠砟砲祕祐祠祟祖神祝祗祚秤 

B 秣秧租秦秩秘窄窈站笆笑粉紡紗紋紊 

C 素索純紐紕級紜納紙紛缺罟羔翅翁耆 

D 耘耕耙耗耽耿胱脂胰脅胭胴脆胸胳脈 

E 能脊胼胯臭臬舀舐航舫舨般芻茫荒荔 

F 荊茸荐草茵茴荏茲茹茶茗荀茱茨荃 


Version 1.3 



B0 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 虔蚊蚪蚓蚤蚩蚌蚣蚜衰衷袁袂衽衹記 

5 訐討訌訕訊託訓訖訏訑豈豺豹財貢起 

6 躬軒軔軏辱送逆迷退迺迴逃追逅迸邕 

7 郡郝郢酒配酌釘針釗釜釙閃院陣陡 

A 陛陝除陘陞隻飢馬骨高鬥鬲鬼乾偺 

B 偽停假偃偌做偉健偶偎偕偵側偷偏倏 

C 偯偭兜冕凰剪副勒務勘動匐匏匙匿區 

D 匾參曼商啪啦啄啞啡啃啊唱啖問啕唯 

E 啤唸售啜唬啣唳啁啗圈國圉域堅堊堆 

F 埠埤基堂堵執培夠奢娶婁婉婦婪婀 

B1 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 娼婢婚婆婊孰寇寅寄寂宿密尉專將屠 

5 屜屝崇崆崎崛崖崢崑崩崔崙崤崧崗巢 

6 常帶帳帷康庸庶庵庾張強彗彬彩彫得 

7 徙從徘御徠徜恿患悉悠您惋悴惦悽 

A 情悻悵惜悼惘惕惆惟悸惚惇戚戛扈 

B 掠控捲掖探接捷捧掘措捱掩掉掃掛捫 

C 推掄授掙採掬排掏掀捻捩捨捺敝敖救 

D 教敗啟敏敘敕敔斜斛斬族旋旌旎晝晚 

E 晤晨晦晞曹勗望梁梯梢梓梵桿桶梱梧 

F 梗械梃棄梭梆梅梔條梨梟梡梂欲殺 

B2 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 毫毬氫涎涼淳淙液淡淌淤添淺清淇淋 

5 涯淑涮淞淹涸混淵淅淒渚涵淚淫淘淪 

6 深淮淨淆淄涪淬涿淦烹焉焊烽烯爽牽 

7 犁猜猛猖猓猙率琅琊球理現琍瓠瓶 

A 瓷甜產略畦畢異疏痔痕疵痊痍皎盔 

B 盒盛眷眾眼眶眸眺硫硃硎祥票祭移窒 

C 窕笠笨笛第符笙笞笮粒粗粕絆絃統紮 

D 紹紼絀細紳組累終紲紱缽羞羚翌翎習 

E 耜聊聆脯脖脣脫脩脰脤舂舵舷舶船莎 

F 莞莘荸莢莖莽莫莒莊莓莉莠荷荻荼 


Version 1.3 



B3 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 莆莧處彪蛇蛀蚶蛄蚵蛆蛋蚱蚯蛉術袞 

5 袈被袒袖袍袋覓規訪訝訣訥許設訟訛 

6 訢豉豚販責貫貨貪貧赧赦趾趺軛軟這 

7 逍通逗連速逝逐逕逞造透逢逖逛途 

A 部郭都酗野釵釦釣釧釭釩閉陪陵陳 

B 陸陰陴陶陷陬雀雪雩章竟頂頃魚鳥鹵 

C 鹿麥麻傢傍傅備傑傀傖傘傚最凱割剴 

D 創剩勞勝勛博厥啻喀喧啼喊喝喘喂喜 

E 喪喔喇喋喃喳單喟唾喲喚喻喬喱啾喉 

F 喫喙圍堯堪場堤堰報堡堝堠壹壺奠 

B4 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 婷媚婿媒媛媧孳孱寒富寓寐尊尋就嵌 

5 嵐崴嵇巽幅帽幀幃幾廊廁廂廄弼彭復 

6 循徨惑惡悲悶惠愜愣惺愕惰惻惴慨惱 

7 愎惶愉愀愒戟扉掣掌描揀揩揉揆揍 

A 插揣提握揖揭揮捶援揪換摒揚揹敞 

B 敦敢散斑斐斯普晰晴晶景暑智晾晷曾 

C 替期朝棺棕棠棘棗椅棟棵森棧棹棒棲 

D 棣棋棍植椒椎棉棚楮棻款欺欽殘殖殼 

E 毯氮氯氬港游湔渡渲湧湊渠渥渣減湛 

F 湘渤湖湮渭渦湯渴湍渺測湃渝渾滋 

B5 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 溉渙湎湣湄湲湩湟焙焚焦焰無然煮焜 

5 牌犄犀猶猥猴猩琺琪琳琢琥琵琶琴琯 

6 琛琦琨甥甦畫番痢痛痣痙痘痞痠登發 

7 皖皓皴盜睏短硝硬硯稍稈程稅稀窘 

A 窗窖童竣等策筆筐筒答筍筋筏筑粟 

B 粥絞結絨絕紫絮絲絡給絢絰絳善翔翕 

C 耋聒肅腕腔腋腑腎脹腆脾腌腓腴舒舜 

D 菩萃菸萍菠菅萋菁華菱菴著萊菰萌菌 

E 菽菲菊萸萎萄菜萇菔菟虛蛟蛙蛭蛔蛛 

F 蛤蛐蛞街裁裂袱覃視註詠評詞証詁 


Version 1.3 



B6 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 詔詛詐詆訴診訶詖象貂貯貼貳貽賁費 

5 賀貴買貶貿貸越超趁跎距跋跚跑跌跛 

6 跆軻軸軼辜逮逵週逸進逶鄂郵鄉郾酣 

7 酥量鈔鈕鈣鈉鈞鈍鈐鈇鈑閔閏開閑 

A 間閒閎隊階隋陽隅隆隍陲隄雁雅雄 

B 集雇雯雲韌項順須飧飪飯飩飲飭馮馭 

C 黃黍黑亂傭債傲傳僅傾催傷傻傯僇剿 

D 剷剽募勦勤勢勣匯嗟嗨嗓嗦嗎嗜嗇嗑 

E 嗣嗤嗯嗚嗡嗅嗆嗥嗉園圓塞塑塘塗塚 

F 塔填塌塭塊塢塒塋奧嫁嫉嫌媾媽媼 

B7 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 媳嫂媲嵩嵯幌幹廉廈弒彙徬微愚意慈 

5 感想愛惹愁愈慎慌慄慍愾愴愧愍愆愷 

6 戡戢搓搾搞搪搭搽搬搏搜搔損搶搖搗 

7 搆敬斟新暗暉暇暈暖暄暘暍會榔業 

A 楚楷楠楔極椰概楊楨楫楞楓楹榆楝 

B 楣楛歇歲毀殿毓毽溢溯滓溶滂源溝滇 

C 滅溥溘溼溺溫滑準溜滄滔溪溧溴煎煙 

D 煩煤煉照煜煬煦煌煥煞煆煨煖爺牒猷 

E 獅猿猾瑯瑚瑕瑟瑞瑁琿瑙瑛瑜當畸瘀 

F 痰瘁痲痱痺痿痴痳盞盟睛睫睦睞督 

B8 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 睹睪睬睜睥睨睢矮碎碰碗碘碌碉硼碑 

5 碓硿祺祿禁萬禽稜稚稠稔稟稞窟窠筷 

6 節筠筮筧粱粳粵經絹綑綁綏絛置罩罪 

7 署義羨群聖聘肆肄腱腰腸腥腮腳腫 

A 腹腺腦舅艇蒂葷落萱葵葦葫葉葬葛 

B 萼萵葡董葩葭葆虞虜號蛹蜓蜈蜇蜀蛾 

C 蛻蜂蜃蜆蜊衙裟裔裙補裘裝裡裊裕裒 

D 覜解詫該詳試詩詰誇詼詣誠話誅詭詢 

E 詮詬詹詻訾詨豢貊貉賊資賈賄貲賃賂 

F 賅跡跟跨路跳跺跪跤跦躲較載軾輊 


Version 1.3 



B9 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 辟農運遊道遂達逼違遐遇遏過遍遑逾 

5 遁鄒鄗酬酪酩釉鈷鉗鈸鈽鉀鈾鉛鉋鉤 

6 鉑鈴鉉鉍鉅鈹鈿鉚閘隘隔隕雍雋雉雊 

7 雷電雹零靖靴靶預頑頓頊頒頌飼飴 

A 飽飾馳馱馴髡鳩麂鼎鼓鼠僧僮僥僖 

B 僭僚僕像僑僱僎僩兢凳劃劂匱厭嗾嘀 

C 嘛嘗嗽嘔嘆嘉嘍嘎嗷嘖嘟嘈嘐嗶團圖 

D 塵塾境墓墊塹墅塽壽夥夢夤奪奩嫡嫦 

E 嫩嫗嫖嫘嫣孵寞寧寡寥實寨寢寤察對 

F 屢嶄嶇幛幣幕幗幔廓廖弊彆彰徹慇 

BA 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 愿態慷慢慣慟慚慘慵截撇摘摔撤摸摟 

5 摺摑摧搴摭摻敲斡旗旖暢暨暝榜榨榕 

6 槁榮槓構榛榷榻榫榴槐槍榭槌榦槃榣 

7 歉歌氳漳演滾漓滴漩漾漠漬漏漂漢 

A 滿滯漆漱漸漲漣漕漫漯澈漪滬漁滲 

B 滌滷熔熙煽熊熄熒爾犒犖獄獐瑤瑣瑪 

C 瑰瑭甄疑瘧瘍瘋瘉瘓盡監瞄睽睿睡磁 

D 碟碧碳碩碣禎福禍種稱窪窩竭端管箕 

E 箋筵算箝箔箏箸箇箄粹粽精綻綰綜綽 

F 綾綠緊綴網綱綺綢綿綵綸維緒緇綬 

BB 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 罰翠翡翟聞聚肇腐膀膏膈膊腿膂臧臺 

5 與舔舞艋蓉蒿蓆蓄蒙蒞蒲蒜蓋蒸蓀蓓 

6 蒐蒼蓑蓊蜿蜜蜻蜢蜥蜴蜘蝕蜷蜩裳褂 

7 裴裹裸製裨褚裯誦誌語誣認誡誓誤 

A 說誥誨誘誑誚誧豪貍貌賓賑賒赫趙 

B 趕跼輔輒輕輓辣遠遘遜遣遙遞遢遝遛 

C 鄙鄘鄞酵酸酷酴鉸銀銅銘銖鉻銓銜銨 

D 鉼銑閡閨閩閣閥閤隙障際雌雒需靼鞅 

E 韶頗領颯颱餃餅餌餉駁骯骰髦魁魂鳴 

F 鳶鳳麼鼻齊億儀僻僵價儂儈儉儅凜 


Version 1.3 



BC 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 劇劈劉劍劊勰厲嘮嘻嘹嘲嘿嘴嘩噓噎 

5 噗噴嘶嘯嘰墀墟增墳墜墮墩墦奭嬉嫻 

6 嬋嫵嬌嬈寮寬審寫層履嶝嶔幢幟幡廢 

7 廚廟廝廣廠彈影德徵慶慧慮慝慕憂 

A 慼慰慫慾憧憐憫憎憬憚憤憔憮戮摩 

B 摯摹撞撲撈撐撰撥撓撕撩撒撮播撫撚 

C 撬撙撢撳敵敷數暮暫暴暱樣樟槨樁樞 

D 標槽模樓樊槳樂樅槭樑歐歎殤毅毆漿 

E 潼澄潑潦潔澆潭潛潸潮澎潺潰潤澗潘 

F 滕潯潠潟熟熬熱熨牖犛獎獗瑩璋璃 

BD 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 瑾璀畿瘠瘩瘟瘤瘦瘡瘢皚皺盤瞎瞇瞌 

5 瞑瞋磋磅確磊碾磕碼磐稿稼穀稽稷稻 

6 窯窮箭箱範箴篆篇篁箠篌糊締練緯緻 

7 緘緬緝編緣線緞緩綞緙緲緹罵罷羯 

A 翩耦膛膜膝膠膚膘蔗蔽蔚蓮蔬蔭蔓 

B 蔑蔣蔡蔔蓬蔥蓿蔆螂蝴蝶蝠蝦蝸蝨蝙 

C 蝗蝌蝓衛衝褐複褒褓褕褊誼諒談諄誕 

D 請諸課諉諂調誰論諍誶誹諛豌豎豬賠 

E 賞賦賤賬賭賢賣賜質賡赭趟趣踫踐踝 

F 踢踏踩踟踡踞躺輝輛輟輩輦輪輜輞 

BE 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 輥適遮遨遭遷鄰鄭鄧鄱醇醉醋醃鋅銻 

5 銷鋪銬鋤鋁銳銼鋒鋇鋰銲閭閱霄霆震 

6 霉靠鞍鞋鞏頡頫頜颳養餓餒餘駝駐駟 

7 駛駑駕駒駙骷髮髯鬧魅魄魷魯鴆鴉 

A 鴃麩麾黎墨齒儒儘儔儐儕冀冪凝劑 

B 劓勳噙噫噹噩噤噸噪器噥噱噯噬噢噶 

C 壁墾壇壅奮嬝嬴學寰導彊憲憑憩憊懍 

D 憶憾懊懈戰擅擁擋撻撼據擄擇擂操撿 

E 擒擔撾整曆曉暹曄曇暸樽樸樺橙橫橘 

F 樹橄橢橡橋橇樵機橈歙歷氅濂澱澡 


Version 1.3 



BF 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 濃澤濁澧澳激澹澶澦澠澴熾燉燐燒燈 

5 燕熹燎燙燜燃燄獨璜璣璘璟璞瓢甌甍 

6 瘴瘸瘺盧盥瞠瞞瞟瞥磨磚磬磧禦積穎 

7 穆穌穋窺篙簑築篤篛篡篩篦糕糖縊 

A 縑縈縛縣縞縝縉縐罹羲翰翱翮耨膳 

B 膩膨臻興艘艙蕊蕙蕈蕨蕩蕃蕉蕭蕪蕞 

C 螃螟螞螢融衡褪褲褥褫褡親覦諦諺諫 

D 諱謀諜諧諮諾謁謂諷諭諳諶諼豫豭貓 

E 賴蹄踱踴蹂踹踵輻輯輸輳辨辦遵遴選 

F 遲遼遺鄴醒錠錶鋸錳錯錢鋼錫錄錚 

C0 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 錐錦錡錕錮錙閻隧隨險雕霎霑霖霍霓 

5 霏靛靜靦鞘頰頸頻頷頭頹頤餐館餞餛 

6 餡餚駭駢駱骸骼髻髭鬨鮑鴕鴣鴦鴨鴒 

7 鴛默黔龍龜優償儡儲勵嚎嚀嚐嚅嚇 

A 嚏壕壓壑壎嬰嬪嬤孺尷屨嶼嶺嶽嶸 

B 幫彌徽應懂懇懦懋戲戴擎擊擘擠擰擦 

C 擬擱擢擭斂斃曙曖檀檔檄檢檜櫛檣橾 

D 檗檐檠歜殮毚氈濘濱濟濠濛濤濫濯澀 

E 濬濡濩濕濮濰燧營燮燦燥燭燬燴燠爵 

F 牆獰獲璩環璦璨癆療癌盪瞳瞪瞰瞬 

C1 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 瞧瞭矯磷磺磴磯礁禧禪穗窿簇簍篾篷 

5 簌篠糠糜糞糢糟糙糝縮績繆縷縲繃縫 

6 總縱繅繁縴縹繈縵縿縯罄翳翼聱聲聰 

7 聯聳臆臃膺臂臀膿膽臉膾臨舉艱薪 

A 薄蕾薜薑薔薯薛薇薨薊虧蟀蟑螳蟒 

B 蟆螫螻螺蟈蟋褻褶襄褸褽覬謎謗謙講 

C 謊謠謝謄謐豁谿豳賺賽購賸賻趨蹉蹋 

D 蹈蹊轄輾轂轅輿避遽還邁邂邀鄹醣醞 

E 醜鍍鎂錨鍵鍊鍥鍋錘鍾鍬鍛鍰鍚鍔闊 

F 闋闌闈闆隱隸雖霜霞鞠韓顆颶餵騁 


Version 1.3 



C2 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 駿鮮鮫鮪鮭鴻鴿麋黏點黜黝黛鼾齋叢 

5 嚕嚮壙壘嬸彝懣戳擴擲擾攆擺擻擷斷 

6 曜朦檳檬櫃檻檸櫂檮檯歟歸殯瀉瀋濾 

7 瀆濺瀑瀏燻燼燾燸獷獵璧璿甕癖癘 

A 癒瞽瞿瞻瞼礎禮穡穢穠竄竅簫簧簪 

B 簞簣簡糧織繕繞繚繡繒繙罈翹翻職聶 

C 臍臏舊藏薩藍藐藉薰薺薹薦蟯蟬蟲蟠 

D 覆覲觴謨謹謬謫豐贅蹙蹣蹦蹤蹟蹕軀 

E 轉轍邇邃邈醫醬釐鎔鎊鎖鎢鎳鎮鎬鎰 

F 鎘鎚鎗闔闖闐闕離雜雙雛雞霤鞣鞦 

C3 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 鞭韹額顏題顎顓颺餾餿餽餮馥騎髁鬃 

5 鬆魏魎魍鯊鯉鯽鯈鯀鵑鵝鵠黠鼕鼬儳 

6 嚥壞壟壢寵龐廬懲懷懶懵攀攏曠曝櫥 

7 櫝櫚櫓瀛瀟瀨瀚瀝瀕瀘爆爍牘犢獸 

A 獺璽瓊瓣疇疆癟癡矇礙禱穫穩簾簿 

B 簸簽簷籀繫繭繹繩繪羅繳羶羹羸臘藩 

C 藝藪藕藤藥藷蟻蠅蠍蟹蟾襠襟襖襞譁 

D 譜識證譚譎譏譆譙贈贊蹼蹲躇蹶蹬蹺 

E 蹴轔轎辭邊邋醱醮鏡鏑鏟鏃鏈鏜鏝鏖 

F 鏢鏍鏘鏤鏗鏨關隴難霪霧靡韜韻類 

C4 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 願顛颼饅饉騖騙鬍鯨鯧鯖鯛鶉鵡鵲鵪 

5 鵬麒麗麓麴勸嚨嚷嚶嚴嚼壤孀孃孽寶 

6 巉懸懺攘攔攙曦朧櫬瀾瀰瀲爐獻瓏癢 

7 癥礦礪礬礫竇競籌籃籍糯糰辮繽繼 

A 纂罌耀臚艦藻藹蘑藺蘆蘋蘇蘊蠔蠕 

B 襤覺觸議譬警譯譟譫贏贍躉躁躅躂醴 

C 釋鐘鐃鏽闡霰飄饒饑馨騫騰騷騵鰓鰍 

D 鹹麵黨鼯齟齣齡儷儸囁囀囂夔屬巍懼 

E 懾攝攜斕曩櫻欄櫺殲灌爛犧瓖瓔癩矓 

F 籐纏續羼蘗蘭蘚蠣蠢蠡蠟襪襬覽譴 


Version 1.3 



C5 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 護譽贓躊躍躋轟辯醺鐮鐳鐵鐺鐸鐲鐫 

5 闢霸霹露響顧顥饗驅驃驀騾髏魔魑鰭 

6 鰥鶯鶴鷂鶸麝黯鼙齜齦齧儼儻囈囊囉 

7 孿巔巒彎懿攤權歡灑灘玀瓤疊癮癬 

A 禳籠籟聾聽臟襲襯觼讀贖贗躑躓轡 

B 酈鑄鑑鑒霽霾韃韁顫饕驕驍髒鬚鱉鰱 

C 鰾鰻鷓鷗鼴齬齪龔囌巖戀攣攫攪曬欐 

D 瓚竊籤籣籥纓纖纔臢蘸蘿蠱變邐邏鑣 

E 鑠鑤靨顯饜驚驛驗髓體髑鱔鱗鱖鷥麟 

F 黴囑壩攬灞癱癲矗罐羈蠶蠹衢讓讒 

C6 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 讖艷贛釀鑪靂靈靄韆顰驟鬢魘鱟鷹鷺 

5 鹼鹽鼇齷齲廳欖灣籬籮蠻觀躡釁鑲鑰 

6 顱饞髖鬣黌灤矚讚鑷韉驢驥纜讜躪釅 

7 鑽鑾鑼鱷鱸黷豔鑿鸚爨驪鬱鸛鸞籲 

A 

B 

ヽ 

C 

D ヽヾゝゞ〃 

E 々〆〇ーぁあぃいぅうぇえぉ 

F おかがきぎくぐけげこごさざしじ 

C7 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 すずせぜそぞただちぢっつづてでと 

5 どなにぬねのはばぱひびぴふぶぷへ 

6 べぺほぼぽまみむめもゃやゅゆょよ 

7 らりるれろゎわゐゑをんァアィイ 

A ゥウェエォオカガキギクグケゲコ 

B ゴサザシジスズセゼソゾタダチヂッ 

C ツヅテデトドナニヌネノハバパヒビ 

D ピフブプヘベペホボポマミムメモャ 

E ヤュユョヨラリルレロヮワヰヱヲン 

F ヴヵヶ 


Version 1.3 



C8 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 

5 

6 

7 

A 

B 

C 

D 

E 

F 

C9 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 乂乜凵匚厂万丌乇亍囗兀屮彳丏冇与 

5 丮亓仂仉仈冘勼卬厹圠夃夬尐巿旡殳 

6 毌气爿丱丼仨仜仩仡仝仚刌匜卌圢圣 

7 夗夯宁宄尒尻屴屳帄庀庂忉戉扐氕 

A 氶汃氿氻犮犰玊禸肊阞伎优伬仵伔 

B 仱伀价伈伝伂伅伢伓伄仴伒冱刓刉刐 

C 劦匢匟卍厊吇囡囟圮圪圴夼妀奼妅奻 

D 奾奷奿孖尕尥屼屺屻屾巟幵庄异弚彴 

E 忕忔忏扜扞扤扡扦扢扙扠扚扥旯旮朾 

F 朹朸朻机朿朼朳氘汆汒汜汏汊汔汋 

CA 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 汌灱牞犴犵玎甪癿穵网艸艼芀艽艿虍 

5 襾邙邗邘邛邔阢阤阠阣佖伻佢佉体佤 

6 伾佧佒佟佁佘伭伳伿佡冏冹刜刞刡劭 

7 劮匉卣卲厎厏吰吷吪呔呅吙吜吥吘 

A 吽呏呁吨吤呇囮囧囥坁坅坌坉坋坒 

B 夆奀妦妘妠妗妎妢妐妏妧妡宎宒尨尪 

C 岍岏岈岋岉岒岊岆岓岕巠帊帎庋庉庌 

D 庈庍弅弝彸彶忒忑忐忭忨忮忳忡忤忣 

E 忺忯忷忻怀忴戺抃抌抎抏抔抇扱扻扺 

F 扰抁抈扷扽扲扴攷旰旴旳旲旵杅杇 


Version 1.3 



CB 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 杙杕杌杈杝杍杚杋毐氙氚汸汧汫沄沋 

5 沏汱汯汩沚汭沇沕沜汦汳汥汻沎灴灺 

6 牣犿犽狃狆狁犺狅玕玗玓玔玒町甹疔 

7 疕皁礽耴肕肙肐肒肜芐芏芅芎芑芓 

A 芊芃芄豸迉辿邟邡邥邞邧邠阰阨阯 

B 阭丳侘佼侅佽侀侇佶佴侉侄佷佌侗佪 

C 侚佹侁佸侐侜侔侞侒侂侕佫佮冞冼冾 

D 刵刲刳剆刱劼匊匋匼厒厔咇呿咁咑咂 

E 咈呫呺呾呥呬呴呦咍呯呡呠咘呣呧呤 

F 囷囹坯坲坭坫坱坰坶垀坵坻坳坴坢 

CC 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 坨坽夌奅妵妺姏姎妲姌姁妶妼姃姖妱 

5 妽姀姈妴姇孢孥宓宕屄屇岮岤岠岵岯 

6 岨岬岟岣岭岢岪岧岝岥岶岰岦帗帔帙 

7 弨弢弣弤彔徂彾彽忞忥怭怦怙怲怋 

A 怴怊怗怳怚怞怬怢怍怐怮怓怑怌怉 

B 怜戔戽抭抴拑抾抪抶拊抮抳抯抻抩抰 

C 抸攽斨斻昉旼昄昒昈旻昃昋昍昅旽昑 

D 昐曶朊枅杬枎枒杶杻枘枆构杴枍枌杺 

E 枟枑枙枃杽极杸杹枔欥殀歾毞氝沓泬 

F 泫泮泙沶泔沭泧沷泐泂沺泃泆泭泲 

CD 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 泒泝沴沊沝沀泞泀洰泍泇沰泹泏泩泑 

5 炔炘炅炓炆炄炑炖炂炚炃牪狖狋狘狉 

6 狜狒狔狚狌狑玤玡玭玦玢玠玬玝瓝瓨 

7 甿畀甾疌疘皯盳盱盰盵矸矼矹矻矺 

A 矷祂礿秅穸穻竻籵糽耵肏肮肣肸肵 

B 肭舠芠苀芫芚芘芛芵芧芮芼芞芺芴芨 

C 芡芩苂芤苃芶芢虰虯虭虮豖迒迋迓迍 

D 迖迕迗邲邴邯邳邰阹阽阼阺陃俍俅俓 

E 侲俉俋俁俔俜俙侻侳俛俇俖侺俀侹俬 

F 剄剉勀勂匽卼厗厖厙厘咺咡咭咥哏 


Version 1.3 



CE 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 哃茍咷咮哖咶哅哆咠呰咼咢咾呲哞咰 

5 垵垞垟垤垌垗垝垛垔垘垏垙垥垚垕壴 

6 复奓姡姞姮娀姱姝姺姽姼姶姤姲姷姛 

7 姩姳姵姠姾姴姭宨屌峐峘峌峗峋峛 

A 峞峚峉峇峊峖峓峔峏峈峆峎峟峸巹 

B 帡帢帣帠帤庰庤庢庛庣庥弇弮彖徆怷 

C 怹恔恲恞恅恓恇恉恛恌恀恂恟怤恄恘 

D 恦恮扂扃拏挍挋拵挎挃拫拹挏挌拸拶 

E 挀挓挔拺挕拻拰敁敃斪斿昶昡昲昵昜 

F 昦昢昳昫昺昝昴昹昮朏朐柁柲柈枺 

CF 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 柜枻柸柘柀枷柅柫柤柟枵柍枳柷柶柮 

5 柣柂枹柎柧柰枲柼柆柭柌枮柦柛柺柉 

6 柊柃柪柋欨殂殄殶毖毘毠氠氡洨洴洭 

7 洟洼洿洒洊泚洳洄洙洺洚洑洀洝浂 

A 洁洘洷洃洏浀洇洠洬洈洢洉洐炷炟 

B 炾炱炰炡炴炵炩牁牉牊牬牰牳牮狊狤 

C 狨狫狟狪狦狣玅珌珂珈珅玹玶玵玴珫 

D 玿珇玾珃珆玸珋瓬瓮甮畇畈疧疪癹盄 

E 眈眃眄眅眊盷盻盺矧矨砆砑砒砅砐砏 

F 砎砉砃砓祊祌祋祅祄秕种秏秖秎窀 

D0 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 穾竑笀笁籺籸籹籿粀粁紃紈紁罘羑羍 

5 羾耇耎耏耔耷胘胇胠胑胈胂胐胅胣胙 

6 胜胊胕胉胏胗胦胍臿舡芔苙苾苹茇苨 

7 茀苕茺苫苖苴苬苡苲苵茌苻苶苰苪 

A 苤苠苺苳苭虷虴虼虳衁衎衧衪衩觓 

B 訄訇赲迣迡迮迠郱邽邿郕郅邾郇郋郈 

C 釔釓陔陏陑陓陊陎倞倅倇倓倢倰倛俵 

D 俴倳倷倬俶俷倗倜倠倧倵倯倱倎党冔 

E 冓凊凄凅凈凎剡剚剒剞剟剕剢勍匎厞 

F 唦哢唗唒哧哳哤唚哿唄唈哫唑唅哱 


Version 1.3 



D1 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 唊哻哷哸哠唎唃唋圁圂埌堲埕埒垺埆 

5 垽垼垸垶垿埇埐垹埁夎奊娙娖娭娮娕 

6 娏娗娊娞娳孬宧宭宬尃屖屔峬峿峮峱 

7 峷崀峹帩帨庨庮庪庬弳弰彧恝恚恧 

A 恁悢悈悀悒悁悝悃悕悛悗悇悜悎戙 

B 扆拲挐捖挬捄捅挶捃揤挹捋捊挼挩捁 

C 挴捘捔捙挭捇挳捚捑挸捗捀捈敊敆旆 

D 旃旄旂晊晟晇晑朒朓栟栚桉栲栳栻桋 

E 桏栖栱栜栵栫栭栯桎桄栴栝栒栔栦栨 

F 栮桍栺栥栠欬欯欭欱欴歭肂殈毦毤 

D2 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 毨毣毢毧氥浺浣浤浶洍浡涒浘浢浭浯 

5 涑涍淯浿涆浞浧浠涗浰浼浟涂涘洯浨 

6 涋浾涀涄洖涃浻浽浵涐烜烓烑烝烋缹 

7 烢烗烒烞烠烔烍烅烆烇烚烎烡牂牸 

A 牷牶猀狺狴狾狶狳狻猁珓珙珥珖玼 

B 珧珣珩珜珒珛珔珝珚珗珘珨瓞瓟瓴瓵 

C 甡畛畟疰痁疻痄痀疿疶疺皊盉眝眛眐 

D 眓眒眣眑眕眙眚眢眧砣砬砢砵砯砨砮 

E 砫砡砩砳砪砱祔祛祏祜祓祒祑秫秬秠 

F 秮秭秪秜秞秝窆窉窅窋窌窊窇竘笐 

D3 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 笄笓笅笏笈笊笎笉笒粄粑粊粌粈粍粅 

5 紞紝紑紎紘紖紓紟紒紏紌罜罡罞罠罝 

6 罛羖羒翃翂翀耖耾耹胺胲胹胵脁胻脀 

7 舁舯舥茳茭荄茙荑茥荖茿荁茦茜茢 

A 荂荎茛茪茈茼荍茖茤茠茷茯茩荇荅 

B 荌荓茞茬荋茧荈虓虒蚢蚨蚖蚍蚑蚞蚇 

C 蚗蚆蚋蚚蚅蚥蚙蚡蚧蚕蚘蚎蚝蚐蚔衃 

D 衄衭衵衶衲袀衱衿衯袃衾衴衼訒豇豗 

E 豻貤貣赶赸趵趷趶軑軓迾迵适迿迻逄 

F 迼迶郖郠郙郚郣郟郥郘郛郗郜郤酐 


Version 1.3 



D4 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 酎酏釕釢釚陜陟隼飣髟鬯乿偰偪偡偞 

5 偠偓偋偝偲偈偍偁偛偊偢倕偅偟偩偫 

6 偣偤偆偀偮偳偗偑凐剫剭剬剮勖勓匭 

7 厜啵啶唼啍啐唴唪啑啢唶唵唰啒啅 

A 唌唲啥啎唹啈唭唻啀啋圊圇埻堔埢 

B 埶埜埴堀埭埽堈埸堋埳埏堇埮埣埲埥 

C 埬埡堎埼堐埧堁堌埱埩埰堍堄奜婠婘 

D 婕婧婞娸娵婭婐婟婥婬婓婤婗婃婝婒 

E 婄婛婈媎娾婍娹婌婰婩婇婑婖婂婜孲 

F 孮寁寀屙崞崋崝崚崠崌崨崍崦崥崏 

D5 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 崰崒崣崟崮帾帴庱庴庹庲庳弶弸徛徖 

5 徟悊悐悆悾悰悺惓惔惏惤惙惝惈悱惛 

6 悷惊悿惃惍惀挲捥掊掂捽掽掞掭掝掗 

7 掫掎捯掇掐据掯捵掜捭掮捼掤挻掟 

A 捸掅掁掑掍捰敓旍晥晡晛晙晜晢朘 

B 桹梇梐梜桭桮梮梫楖桯梣梬梩桵桴梲 

C 梏桷梒桼桫桲梪梀桱桾梛梖梋梠梉梤 

D 桸桻梑梌梊桽欶欳欷欸殑殏殍殎殌氪 

E 淀涫涴涳湴涬淩淢涷淶淔渀淈淠淟淖 

F 涾淥淜淝淛淴淊涽淭淰涺淕淂淏淉 

D6 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 淐淲淓淽淗淍淣涻烺焍烷焗烴焌烰焄 

5 烳焐烼烿焆焓焀烸烶焋焂焎牾牻牼牿 

6 猝猗猇猑猘猊猈狿猏猞玈珶珸珵琄琁 

7 珽琇琀珺珼珿琌琋珴琈畤畣痎痒痏 

A 痋痌痑痐皏皉盓眹眯眭眱眲眴眳眽 

B 眥眻眵硈硒硉硍硊硌砦硅硐祤祧祩祪 

C 祣祫祡离秺秸秶秷窏窔窐笵筇笴笥笰 

D 笢笤笳笘笪笝笱笫笭笯笲笸笚笣粔粘 

E 粖粣紵紽紸紶紺絅紬紩絁絇紾紿絊紻 

F 紨罣羕羜羝羛翊翋翍翐翑翇翏翉耟 


Version 1.3 



D7 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 耞耛聇聃聈脘脥脙脛脭脟脬脞脡脕脧 

5 脝脢舑舸舳舺舴舲艴莐莣莨莍荺荳莤 

6 荴莏莁莕莙荵莔莩荽莃莌莝莛莪莋荾 

7 莥莯莈莗莰荿莦莇莮荶莚虙虖蚿蚷 

A 蛂蛁蛅蚺蚰蛈蚹蚳蚸蛌蚴蚻蚼蛃蚽 

B 蚾衒袉袕袨袢袪袚袑袡袟袘袧袙袛袗 

C 袤袬袌袓袎覂觖觙觕訰訧訬訞谹谻豜 

D 豝豽貥赽赻赹趼跂趹趿跁軘軞軝軜軗 

E 軠軡逤逋逑逜逌逡郯郪郰郴郲郳郔郫 

F 郬郩酖酘酚酓酕釬釴釱釳釸釤釹釪 

D8 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 釫釷釨釮镺閆閈陼陭陫陱陯隿靪頄飥 

5 馗傛傕傔傞傋傣傃傌傎傝偨傜傒傂傇 

6 兟凔匒匑厤厧喑喨喥喭啷噅喢喓喈喏 

7 喵喁喣喒喤啽喌喦啿喕喡喎圌堩堷 

A 堙堞堧堣堨埵塈堥堜堛堳堿堶堮堹 

B 堸堭堬堻奡媯媔媟婺媢媞婸媦婼媥媬 

C 媕媮娷媄媊媗媃媋媩婻婽媌媜媏媓媝 

D 寪寍寋寔寑寊寎尌尰崷嵃嵫嵁嵋崿崵 

E 嵑嵎嵕崳崺嵒崽崱嵙嵂崹嵉崸崼崲崶 

F 嵀嵅幄幁彘徦徥徫惉悹惌惢惎惄愔 

D9 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 惲愊愖愅惵愓惸惼惾惁愃愘愝愐惿愄 

5 愋扊掔掱掰揎揥揨揯揃撝揳揊揠揶揕 

6 揲揵摡揟掾揝揜揄揘揓揂揇揌揋揈揰 

7 揗揙攲敧敪敤敜敨敥斌斝斞斮旐旒 

A 晼晬晻暀晱晹晪晲朁椌棓椄棜椪棬 

B 棪棱椏棖棷棫棤棶椓椐棳棡椇棌椈楰 

C 梴椑棯棆椔棸棐棽棼棨椋椊椗棎棈棝 

D 棞棦棴棑椆棔棩椕椥棇欹欻欿欼殔殗 

E 殙殕殽毰毲毳氰淼湆湇渟湉溈渼渽湅 

F 湢渫渿湁湝湳渜渳湋湀湑渻渃渮湞 


Version 1.3 



DA 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 湨湜湡渱渨湠湱湫渹渢渰湓湥渧湸湤 

5 湷湕湹湒湦渵渶湚焠焞焯烻焮焱焣焥 

6 焢焲焟焨焺焛牋牚犈犉犆犅犋猒猋猰 

7 猢猱猳猧猲猭猦猣猵猌琮琬琰琫琖 

A 琚琡琭琱琤琣琝琩琠琲瓻甯畯畬痧 

B 痚痡痦痝痟痤痗皕皒盚睆睇睄睍睅睊 

C 睎睋睌矞矬硠硤硥硜硭硱硪确硰硩硨 

D 硞硢祴祳祲祰稂稊稃稌稄窙竦竤筊笻 

E 筄筈筌筎筀筘筅粢粞粨粡絘絯絣絓絖 

F 絧絪絏絭絜絫絒絔絩絑絟絎缾缿罥 

DB 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 罦羢羠羡翗聑聏聐胾胔腃腊腒腏腇脽 

5 腍脺臦臮臷臸臹舄舼舽舿艵茻菏菹萣 

6 菀菨萒菧菤菼菶萐菆菈菫菣莿萁菝菥 

7 菘菿菡菋菎菖菵菉萉萏菞萑萆菂菳 

A 菕菺菇菑菪萓菃菬菮菄菻菗菢萛菛 

B 菾蛘蛢蛦蛓蛣蛚蛪蛝蛫蛜蛬蛩蛗蛨蛑 

C 衈衖衕袺裗袹袸裀袾袶袼袷袽袲褁裉 

D 覕覘覗觝觚觛詎詍訹詙詀詗詘詄詅詒 

E 詈詑詊詌詏豟貁貀貺貾貰貹貵趄趀趉 

F 跘跓跍跇跖跜跏跕跙跈跗跅軯軷軺 

DC 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 軹軦軮軥軵軧軨軶軫軱軬軴軩逭逴逯 

5 鄆鄬鄄郿郼鄈郹郻鄁鄀鄇鄅鄃酡酤酟 

6 酢酠鈁鈊鈥鈃鈚鈦鈏鈌鈀鈒釿釽鈆鈄 

7 鈧鈂鈜鈤鈙鈗鈅鈖镻閍閌閐隇陾隈 

A 隉隃隀雂雈雃雱雰靬靰靮頇颩飫鳦 

B 黹亃亄亶傽傿僆傮僄僊傴僈僂傰僁傺 

C 傱僋僉傶傸凗剺剸剻剼嗃嗛嗌嗐嗋嗊 

D 嗝嗀嗔嗄嗩喿嗒喍嗏嗕嗢嗖嗈嗲嗍嗙 

E 嗂圔塓塨塤塏塍塉塯塕塎塝塙塥塛堽 

F 塣塱壼嫇嫄嫋媺媸媱媵媰媿嫈媻嫆 


Version 1.3 



DD 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 媷嫀嫊媴媶嫍媹媐寖寘寙尟尳嵱嵣嵊 

5 嵥嵲嵬嵞嵨嵧嵢巰幏幎幊幍幋廅廌廆 

6 廋廇彀徯徭惷慉慊愫慅愶愲愮慆愯慏 

7 愩慀戠酨戣戥戤揅揱揫搐搒搉搠搤 

A 搳摃搟搕搘搹搷搢搣搌搦搰搨摁搵 

B 搯搊搚摀搥搧搋揧搛搮搡搎敯斒旓暆 

C 暌暕暐暋暊暙暔晸朠楦楟椸楎楢楱椿 

D 楅楪椹楂楗楙楺楈楉椵楬椳椽楥棰楸 

E 椴楩楀楯楄楶楘楁楴楌椻楋椷楜楏楑 

F 椲楒椯楻椼歆歅歃歂歈歁殛嗀毻毼 

DE 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 毹毷毸溛滖滈溏滀溟溓溔溠溱溹滆滒 

5 溽滁溞滉溷溰滍溦滏溲溾滃滜滘溙溒 

6 溎溍溤溡溿溳滐滊溗溮溣煇煔煒煣煠 

7 煁煝煢煲煸煪煡煂煘煃煋煰煟煐煓 

A 煄煍煚牏犍犌犑犐犎猼獂猻猺獀獊 

B 獉瑄瑊瑋瑒瑑瑗瑀瑏瑐瑎瑂瑆瑍瑔瓡 

C 瓿瓾瓽甝畹畷榃痯瘏瘃痷痾痼痹痸瘐 

D 痻痶痭痵痽皙皵盝睕睟睠睒睖睚睩睧 

E 睔睙睭矠碇碚碔碏碄碕碅碆碡碃硹碙 

F 碀碖硻祼禂祽祹稑稘稙稒稗稕稢稓 

DF 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 稛稐窣窢窞竫筦筤筭筴筩筲筥筳筱筰 

5 筡筸筶筣粲粴粯綈綆綀綍絿綅絺綎絻 

6 綃絼綌綔綄絽綒罭罫罧罨罬羦羥羧翛 

7 翜耡腤腠腷腜腩腛腢腲朡腞腶腧腯 

A 腄腡舝艉艄艀艂艅蓱萿葖葶葹蒏蒍 

B 葥葑葀蒆葧萰葍葽葚葙葴葳葝蔇葞萷 

C 萺萴葺葃葸萲葅萩菙葋萯葂萭葟葰萹 

D 葎葌葒葯蓅蒎萻葇萶萳葨葾葄萫葠葔 

E 葮葐蜋蜄蛷蜌蛺蛖蛵蝍蛸蜎蜉蜁蛶蜍 

F 蜅裖裋裍裎裞裛裚裌裐覅覛觟觥觤 


Version 1.3 



E0 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 觡觠觢觜触詶誆詿詡訿詷誂誄詵誃誁 

5 詴詺谼豋豊豥豤豦貆貄貅賌赨赩趑趌 

6 趎趏趍趓趔趐趒跰跠跬跱跮跐跩跣跢 

7 跧跲跫跴輆軿輁輀輅輇輈輂輋遒逿 

A 遄遉逽鄐鄍鄏鄑鄖鄔鄋鄎酮酯鉈鉒 

B 鈰鈺鉦鈳鉥鉞銃鈮鉊鉆鉭鉬鉏鉠鉧鉯 

C 鈶鉡鉰鈱鉔鉣鉐鉲鉎鉓鉌鉖鈲閟閜閞 

D 閛隒隓隑隗雎雺雽雸雵靳靷靸靲頏頍 

E 頎颬飶飹馯馲馰馵骭骫魛鳪鳭鳧麀黽 

F 僦僔僗僨僳僛僪僝僤僓僬僰僯僣僠 

E1 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 凘劀劁勩勫匰厬嘧嘕嘌嘒嗼嘏嘜嘁嘓 

5 嘂嗺嘝嘄嗿嗹墉塼墐墘墆墁塿塴墋塺 

6 墇墑墎塶墂墈塻墔墏壾奫嫜嫮嫥嫕嫪 

7 嫚嫭嫫嫳嫢嫠嫛嫬嫞嫝嫙嫨嫟孷寠 

A 寣屣嶂嶀嵽嶆嵺嶁嵷嶊嶉嶈嵾嵼嶍 

B 嵹嵿幘幙幓廘廑廗廎廜廕廙廒廔彄彃 

C 彯徶愬愨慁慞慱慳慒慓慲慬憀慴慔慺 

D 慛慥愻慪慡慖戩戧戫搫摍摛摝摴摶摲 

E 摳摽摵摦撦摎撂摞摜摋摓摠摐摿搿摬 

F 摫摙摥摷敳斠暡暠暟朅朄朢榱榶槉 

E2 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 榠槎榖榰榬榼榑榙榎榧榍榩榾榯榿槄 

5 榽榤槔榹槊榚槏榳榓榪榡榞槙榗榐槂 

6 榵榥槆歊歍歋殞殟殠毃毄毾滎滵滱漃 

7 漥滸漷滻漮漉潎漙漚漧漘漻漒滭漊 

A 漶潳滹滮漭潀漰漼漵滫漇漎潃漅滽 

B 滶漹漜滼漺漟漍漞漈漡熇熐熉熀熅熂 

C 熏煻熆熁熗牄牓犗犕犓獃獍獑獌瑢瑳 

D 瑱瑵瑲瑧瑮甀甂甃畽疐瘖瘈瘌瘕瘑瘊 

E 瘔皸瞁睼瞅瞂睮瞀睯睾瞃碲碪碴碭碨 

F 硾碫碞碥碠碬碢碤禘禊禋禖禕禔禓 


Version 1.3 



E3 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 禗禈禒禐稫穊稰稯稨稦窨窫窬竮箈箜 

5 箊箑箐箖箍箌箛箎箅箘劄箙箤箂粻粿 

6 粼粺綧綷緂綣綪緁緀緅綝緎緄緆緋緌 

7 綯綹綖綼綟綦綮綩綡緉罳翢翣翥翞 

A 耤聝聜膉膆膃膇膍膌膋舕蒗蒤蒡蒟 

B 蒺蓎蓂蒬蒮蒫蒹蒴蓁蓍蒪蒚蒱蓐蒝蒧 

C 蒻蒢蒔蓇蓌蒛蒩蒯蒨蓖蒘蒶蓏蒠蓗蓔 

D 蓒蓛蒰蒑虡蜳蜣蜨蝫蝀蜮蜞蜡蜙蜛蝃 

E 蜬蝁蜾蝆蜠蜲蜪蜭蜼蜒蜺蜱蜵蝂蜦蜧 

F 蜸蜤蜚蜰蜑裷裧裱裲裺裾裮裼裶裻 

E4 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 裰裬裫覝覡覟覞觩觫觨誫誙誋誒誏誖 

5 谽豨豩賕賏賗趖踉踂跿踍跽踊踃踇踆 

6 踅跾踀踄輐輑輎輍鄣鄜鄠鄢鄟鄝鄚鄤 

7 鄡鄛酺酲酹酳銥銤鉶銛鉺銠銔銪銍 

A 銦銚銫鉹銗鉿銣鋮銎銂銕銢鉽銈銡 

B 銊銆銌銙銧鉾銇銩銝銋鈭隞隡雿靘靽 

C 靺靾鞃鞀鞂靻鞄鞁靿韎韍頖颭颮餂餀 

D 餇馝馜駃馹馻馺駂馽駇骱髣髧鬾鬿魠 

E 魡魟鳱鳲鳵麧僿儃儰僸儆儇僶僾儋儌 

F 僽儊劋劌勱勯噈噂噌嘵噁噊噉噆噘 

E5 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 噚噀嘳嘽嘬嘾嘸嘪嘺圚墫墝墱墠墣墯 

5 墬墥墡壿嫿嫴嫽嫷嫶嬃嫸嬂嫹嬁嬇嬅 

6 嬏屧嶙嶗嶟嶒嶢嶓嶕嶠嶜嶡嶚嶞幩幝 

7 幠幜緳廛廞廡彉徲憋憃慹憱憰憢憉 

A 憛憓憯憭憟憒憪憡憍慦憳戭摮摰撖 

B 撠撅撗撜撏撋撊撌撣撟摨撱撘敶敺敹 

C 敻斲斳暵暰暩暲暷暪暯樀樆樗槥槸樕 

D 槱槤樠槿槬槢樛樝槾樧槲槮樔槷槧橀 

E 樈槦槻樍槼槫樉樄樘樥樏槶樦樇槴樖 

F 歑殥殣殢殦氁氀毿氂潁漦潾澇濆澒 


Version 1.3 



E6 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 澍澉澌潢潏澅潚澖潶潬澂潕潲潒潐潗 

5 澔澓潝漀潡潫潽潧澐潓澋潩潿澕潣潷 

6 潪潻熲熯熛熰熠熚熩熵熝熥熞熤熡熪 

7 熜熧熳犘犚獘獒獞獟獠獝獛獡獚獙 

A 獢璇璉璊璆璁瑽璅璈瑼瑹甈甇畾瘥 

B 瘞瘙瘝瘜瘣瘚瘨瘛皜皝皞皛瞍瞏瞉瞈 

C 磍碻磏磌磑磎磔磈磃磄磉禚禡禠禜禢 

D 禛歶稹窲窴窳箷篋箾箬篎箯箹篊箵糅 

E 糈糌糋緷緛緪緧緗緡縃緺緦緶緱緰緮 

F 緟罶羬羰羭翭翫翪翬翦翨聤聧膣膟 

E7 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 膞膕膢膙膗舖艏艓艒艐艎艑蔤蔻蔏蔀 

5 蔩蔎蔉蔍蔟蔊蔧蔜蓻蔫蓺蔈蔌蓴蔪蓲 

6 蔕蓷蓫蓳蓼蔒蓪蓩蔖蓾蔨蔝蔮蔂蓽蔞 

7 蓶蔱蔦蓧蓨蓰蓯蓹蔘蔠蔰蔋蔙蔯虢 

A 蝖蝣蝤蝷蟡蝳蝘蝔蝛蝒蝡蝚蝑蝞蝭 

B 蝪蝐蝎蝟蝝蝯蝬蝺蝮蝜蝥蝏蝻蝵蝢蝧 

C 蝩衚褅褌褔褋褗褘褙褆褖褑褎褉覢覤 

D 覣觭觰觬諏諆誸諓諑諔諕誻諗誾諀諅 

E 諘諃誺誽諙谾豍貏賥賟賙賨賚賝賧趠 

F 趜趡趛踠踣踥踤踮踕踛踖踑踙踦踧 

E8 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 踔踒踘踓踜踗踚輬輤輘輚輠輣輖輗遳 

5 遰遯遧遫鄯鄫鄩鄪鄲鄦鄮醅醆醊醁醂 

6 醄醀鋐鋃鋄鋀鋙銶鋏鋱鋟鋘鋩鋗鋝鋌 

7 鋯鋂鋨鋊鋈鋎鋦鋍鋕鋉鋠鋞鋧鋑鋓 

A 銵鋡鋆銴镼閬閫閮閰隤隢雓霅霈霂 

B 靚鞊鞎鞈韐韏頞頝頦頩頨頠頛頧颲餈 

C 飺餑餔餖餗餕駜駍駏駓駔駎駉駖駘駋 

D 駗駌骳髬髫髳髲髱魆魃魧魴魱魦魶魵 

E 魰魨魤魬鳼鳺鳽鳿鳷鴇鴀鳹鳻鴈鴅鴄 

F 麃黓鼏鼐儜儓儗儚儑凞匴叡噰噠噮 


Version 1.3 



E9 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 噳噦噣噭噲噞噷圜圛壈墽壉墿墺壂墼 

5 壆嬗嬙嬛嬡嬔嬓嬐嬖嬨嬚嬠嬞寯嶬嶱 

6 嶩嶧嶵嶰嶮嶪嶨嶲嶭嶯嶴幧幨幦幯廩 

7 廧廦廨廥彋徼憝憨憖懅憴懆懁懌憺 

A 憿憸憌擗擖擐擏擉撽撉擃擛擳擙攳 

B 敿敼斢曈暾曀曊曋曏暽暻暺曌朣樴橦 

C 橉橧樲橨樾橝橭橶橛橑樨橚樻樿橁橪 

D 橤橐橏橔橯橩橠樼橞橖橕橍橎橆歕歔 

E 歖殧殪殫毈毇氄氃氆澭濋澣濇澼濎濈 

F 潞濄澽澞濊澨瀄澥澮澺澬澪濏澿澸 

EA 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 澢濉澫濍澯澲澰燅燂熿熸燖燀燁燋燔 

5 燊燇燏熽燘熼燆燚燛犝犞獩獦獧獬獥 

6 獫獪瑿璚璠璔璒璕璡甋疀瘯瘭瘱瘽瘳 

7 瘼瘵瘲瘰皻盦瞚瞝瞡瞜瞛瞢瞣瞕瞙 

A 瞗磝磩磥磪磞磣磛磡磢磭磟磠禤穄 

B 穈穇窶窸窵窱窷篞篣篧篝篕篥篚篨篹 

C 篔篪篢篜篫篘篟糒糔糗糐糑縒縡縗縌 

D 縟縠縓縎縜縕縚縢縋縏縖縍縔縥縤罃 

E 罻罼罺羱翯耪耩聬膱膦膮膹膵膫膰膬 

F 膴膲膷膧臲艕艖艗蕖蕅蕫蕍蕓蕡蕘 

EB 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 蕀蕆蕤蕁蕢蕄蕑蕇蕣蔾蕛蕱蕎蕮蕵蕕 

5 蕧蕠薌蕦蕝蕔蕥蕬虣虥虤螛螏螗螓螒 

6 螈螁螖螘蝹螇螣螅螐螑螝螄螔螜螚螉 

7 褞褦褰褭褮褧褱褢褩褣褯褬褟觱諠 

A 諢諲諴諵諝謔諤諟諰諈諞諡諨諿諯 

B 諻貑貒貐賵賮賱賰賳赬赮趥趧踳踾踸 

C 蹀蹅踶踼踽蹁踰踿躽輶輮輵輲輹輷輴 

D 遶遹遻邆郺鄳鄵鄶醓醐醑醍醏錧錞錈 

E 錟錆錏鍺錸錼錛錣錒錁鍆錭錎錍鋋錝 

F 鋺錥錓鋹鋷錴錂錤鋿錩錹錵錪錔錌 


Version 1.3 



EC 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 錋鋾錉錀鋻錖閼闍閾閹閺閶閿閵閽隩 

5 雔霋霒霐鞙鞗鞔韰韸頵頯頲餤餟餧餩 

6 馞駮駬駥駤駰駣駪駩駧骹骿骴骻髶髺 

7 髹髷鬳鮀鮅鮇魼魾魻鮂鮓鮒鮐魺鮕 

A 魽鮈鴥鴗鴠鴞鴔鴩鴝鴘鴢鴐鴙鴟麈 

B 麆麇麮麭黕黖黺鼒鼽儦儥儢儤儠儩勴 

C 嚓嚌嚍嚆嚄嚃噾嚂噿嚁壖壔壏壒嬭嬥 

D 嬲嬣嬬嬧嬦嬯嬮孻寱寲嶷幬幪徾徻懃 

E 憵憼懧懠懥懤懨懞擯擩擣擫擤擨斁斀 

F 斶旚曒檍檖檁檥檉檟檛檡檞檇檓檎 

ED 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 檕檃檨檤檑橿檦檚檅檌檒歛殭氉濌澩 

5 濴濔濣濜濭濧濦濞濲濝濢濨燡燱燨燲 

6 燤燰燢獳獮獯璗璲璫璐璪璭璱璥璯甐 

7 甑甒甏疄癃癈癉癇皤盩瞵瞫瞲瞷瞶 

A 瞴瞱瞨矰磳磽礂磻磼磲礅磹磾礄禫 

B 禨穜穛穖穘穔穚窾竀竁簅簏篲簀篿篻 

C 簎篴簋篳簂簉簃簁篸篽簆篰篱簐簊糨 

D 縭縼繂縳顈縸縪繉繀繇縩繌縰縻縶繄 

E 縺罅罿罾罽翴翲耬膻臄臌臊臅臇膼臩 

F 艛艚艜薃薀薏薧薕薠薋薣蕻薤薚薞 

EE 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 蕷蕼薉薡蕺蕸蕗薎薖薆薍薙薝薁薢薂 

5 薈薅蕹蕶薘薐薟虨螾螪螭蟅螰螬螹螵 

6 螼螮蟉蟃蟂蟌螷螯蟄蟊螴螶螿螸螽蟞 

7 螲褵褳褼褾襁襒褷襂覭覯覮觲觳謞 

A 謘謖謑謅謋謢謏謒謕謇謍謈謆謜謓 

B 謚豏豰豲豱豯貕貔賹赯蹎蹍蹓蹐蹌蹇 

C 轃轀邅遾鄸醚醢醛醙醟醡醝醠鎡鎃鎯 

D 鍤鍖鍇鍼鍘鍜鍶鍉鍐鍑鍠鍭鎏鍌鍪鍹 

E 鍗鍕鍒鍏鍱鍷鍻鍡鍞鍣鍧鎀鍎鍙闇闀 

F 闉闃闅閷隮隰隬霠霟霘霝霙鞚鞡鞜 


Version 1.3 



EF 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 鞞鞝韕韔韱顁顄顊顉顅顃餥餫餬餪餳 

5 餲餯餭餱餰馘馣馡騂駺駴駷駹駸駶駻 

6 駽駾駼騃骾髾髽鬁髼魈鮚鮨鮞鮛鮦鮡 

7 鮥鮤鮆鮢鮠鮯鴳鵁鵧鴶鴮鴯鴱鴸鴰 

A 鵅鵂鵃鴾鴷鵀鴽翵鴭麊麉麍麰黈黚 

B 黻黿鼤鼣鼢齔龠儱儭儮嚘嚜嚗嚚嚝嚙 

C 奰嬼屩屪巀幭幮懘懟懭懮懱懪懰懫懖 

D 懩擿攄擽擸攁攃擼斔旛曚曛曘櫅檹檽 

E 櫡櫆檺檶檷櫇檴檭歞毉氋瀇瀌瀍瀁瀅 

F 瀔瀎濿瀀濻瀦濼濷瀊爁燿燹爃燽獶 

F0 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 璸瓀璵瓁璾璶璻瓂甔甓癜癤癙癐癓癗 

5 癚皦皽盬矂瞺磿礌礓礔礉礐礒礑禭禬 

6 穟簜簩簙簠簟簭簝簦簨簢簥簰繜繐繖 

7 繣繘繢繟繑繠繗繓羵羳翷翸聵臑臒 

A 臐艟艞薴藆藀藃藂薳薵薽藇藄薿藋 

B 藎藈藅薱薶藒蘤薸薷薾虩蟧蟦蟢蟛蟫 

C 蟪蟥蟟蟳蟤蟔蟜蟓蟭蟘蟣螤蟗蟙蠁蟴 

D 蟨蟝襓襋襏襌襆襐襑襉謪謧謣謳謰謵 

E 譇謯謼謾謱謥謷謦謶謮謤謻謽謺豂豵 

F 貙貘貗賾贄贂贀蹜蹢蹠蹗蹖蹞蹥蹧 

F1 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 蹛蹚蹡蹝蹩蹔轆轇轈轋鄨鄺鄻鄾醨醥 

5 醧醯醪鎵鎌鎒鎷鎛鎝鎉鎧鎎鎪鎞鎦鎕 

6 鎈鎙鎟鎍鎱鎑鎲鎤鎨鎴鎣鎥闒闓闑隳 

7 雗雚巂雟雘雝霣霢霥鞬鞮鞨鞫鞤鞪 

A 鞢鞥韗韙韖韘韺顐顑顒颸饁餼餺騏 

B 騋騉騍騄騑騊騅騇騆髀髜鬈鬄鬅鬩鬵 

C 魊魌魋鯇鯆鯃鮿鯁鮵鮸鯓鮶鯄鮹鮽鵜 

D 鵓鵏鵊鵛鵋鵙鵖鵌鵗鵒鵔鵟鵘鵚麎麌 

E 黟鼁鼀鼖鼥鼫鼪鼩鼨齌齕儴儵劖勷厴 

F 嚫嚭嚦嚧嚪嚬壚壝壛夒嬽嬾嬿巃幰 


Version 1.3 



F2 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 徿懻攇攐攍攉攌攎斄旞旝曞櫧櫠櫌櫑 

5 櫙櫋櫟櫜櫐櫫櫏櫍櫞歠殰氌瀙瀧瀠瀖 

6 瀫瀡瀢瀣瀩瀗瀤瀜瀪爌爊爇爂爅犥犦 

7 犤犣犡瓋瓅璷瓃甖癠矉矊矄矱礝礛 

A 礡礜礗礞禰穧穨簳簼簹簬簻糬糪繶 

B 繵繸繰繷繯繺繲繴繨罋罊羃羆羷翽翾 

C 聸臗臕艤艡艣藫藱藭藙藡藨藚藗藬藲 

D 藸藘藟藣藜藑藰藦藯藞藢蠀蟺蠃蟶蟷 

E 蠉蠌蠋蠆蟼蠈蟿蠊蠂襢襚襛襗襡襜襘 

F 襝襙覈覷覶觶譐譈譊譀譓譖譔譋譕 

F3 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 譑譂譒譗豃豷豶貚贆贇贉趬趪趭趫蹭 

5 蹸蹳蹪蹯蹻軂轒轑轏轐轓辴酀鄿醰醭 

6 鏞鏇鏏鏂鏚鏐鏹鏬鏌鏙鎩鏦鏊鏔鏮鏣 

7 鏕鏄鏎鏀鏒鏧镽闚闛雡霩霫霬霨霦 

A 鞳鞷鞶韝韞韟顜顙顝顗颿颽颻颾饈 

B 饇饃馦馧騚騕騥騝騤騛騢騠騧騣騞騜 

C 騔髂鬋鬊鬎鬌鬷鯪鯫鯠鯞鯤鯦鯢鯰鯔 

D 鯗鯬鯜鯙鯥鯕鯡鯚鵷鶁鶊鶄鶈鵱鶀鵸 

E 鶆鶋鶌鵽鵫鵴鵵鵰鵩鶅鵳鵻鶂鵯鵹鵿 

F 鶇鵨麔麑黀黼鼭齀齁齍齖齗齘匷嚲 

F4 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 嚵嚳壣孅巆巇廮廯忀忁懹攗攖攕攓旟 

5 曨曣曤櫳櫰櫪櫨櫹櫱櫮櫯瀼瀵瀯瀷瀴 

6 瀱灂瀸瀿瀺瀹灀瀻瀳灁爓爔犨獽獼璺 

7 皫皪皾盭矌矎矏矍矲礥礣礧礨礤礩 

A 禲穮穬穭竷籉籈籊籇籅糮繻繾纁纀 

B 羺翿聹臛臙舋艨艩蘢藿蘁藾蘛蘀藶蘄 

C 蘉蘅蘌藽蠙蠐蠑蠗蠓蠖襣襦覹觷譠譪 

D 譝譨譣譥譧譭趮躆躈躄轙轖轗轕轘轚 

E 邍酃酁醷醵醲醳鐋鐓鏻鐠鐏鐔鏾鐕鐐 

F 鐨鐙鐍鏵鐀鏷鐇鐎鐖鐒鏺鐉鏸鐊鏿 


Version 1.3 



F5 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 鏼鐌鏶鐑鐆闞闠闟霮霯鞹鞻韽韾顠顢 

5 顣顟飁飂饐饎饙饌饋饓騲騴騱騬騪騶 

6 騩騮騸騭髇髊髆鬐鬒鬑鰋鰈鯷鰅鰒鯸 

7 鱀鰇鰎鰆鰗鰔鰉鶟鶙鶤鶝鶒鶘鶐鶛 

A 鶠鶔鶜鶪鶗鶡鶚鶢鶨鶞鶣鶿鶩鶖鶦 

B 鶧麙麛麚黥黤黧黦鼰鼮齛齠齞齝齙龑 

C 儺儹劘劗囃嚽嚾孈孇巋巏廱懽攛欂櫼 

D 欃櫸欀灃灄灊灈灉灅灆爝爚爙獾甗癪 

E 矐礭礱礯籔籓糲纊纇纈纋纆纍罍羻耰 

F 臝蘘蘪蘦蘟蘣蘜蘙蘧蘮蘡蘠蘩蘞蘥 

F6 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 蠩蠝蠛蠠蠤蠜蠫衊襭襩襮襫觺譹譸譅 

5 譺譻贐贔趯躎躌轞轛轝酆酄酅醹鐿鐻 

6 鐶鐩鐽鐼鐰鐹鐪鐷鐬鑀鐱闥闤闣霵霺 

7 鞿韡顤飉飆飀饘饖騹騽驆驄驂驁騺 

A 騿髍鬕鬗鬘鬖鬺魒鰫鰝鰜鰬鰣鰨鰩 

B 鰤鰡鶷鶶鶼鷁鷇鷊鷏鶾鷅鷃鶻鶵鷎鶹 

C 鶺鶬鷈鶱鶭鷌鶳鷍鶲鹺麜黫黮黭鼛鼘 

D 鼚鼱齎齥齤龒亹囆囅囋奱孋孌巕巑廲 

E 攡攠攦攢欋欈欉氍灕灖灗灒爞爟犩獿 

F 瓘瓕瓙瓗癭皭礵禴穰穱籗籜籙籛籚 

F7 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 糴糱纑罏羇臞艫蘴蘵蘳蘬蘲蘶蠬蠨蠦 

5 蠪蠥襱覿覾觻譾讄讂讆讅譿贕躕躔躚 

6 躒躐躖躗轠轢酇鑌鑐鑊鑋鑏鑇鑅鑈鑉 

7 鑆霿韣顪顩飋饔饛驎驓驔驌驏驈驊 

A 驉驒驐髐鬙鬫鬻魖魕鱆鱈鰿鱄鰹鰳 

B 鱁鰼鰷鰴鰲鰽鰶鷛鷒鷞鷚鷋鷐鷜鷑鷟 

C 鷩鷙鷘鷖鷵鷕鷝麶黰鼵鼳鼲齂齫龕龢 

D 儽劙壨壧奲孍巘蠯彏戁戃戄攩攥斖曫 

E 欑欒欏毊灛灚爢玂玁玃癰矔籧籦纕艬 

F 蘺虀蘹蘼蘱蘻蘾蠰蠲蠮蠳襶襴襳觾 


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F8 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 讌讎讋讈豅贙躘轤轣醼鑢鑕鑝鑗鑞韄 

5 韅頀驖驙鬞鬟鬠鱒鱘鱐鱊鱍鱋鱕鱙鱌 

6 鱎鷻鷷鷯鷣鷫鷸鷤鷶鷡鷮鷦鷲鷰鷢鷬 

7 鷴鷳鷨鷭黂黐黲黳鼆鼜鼸鼷鼶齃齏 

A 齱齰齮齯囓囍孎屭攭曭曮欓灟灡灝 

B 灠爣瓛瓥矕礸禷禶籪纗羉艭虃蠸蠷蠵 

C 衋讔讕躞躟躠躝醾醽釂鑫鑨鑩雥靆靃 

D 靇韇韥驞髕魙鱣鱧鱦鱢鱞鱠鸂鷾鸇鸃 

E 鸆鸅鸀鸁鸉鷿鷽鸄麠鼞齆齴齵齶囔攮 

F 斸欘欙欗欚灢爦犪矘矙礹籩籫糶纚 

F9 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 纘纛纙臠臡虆虇虈襹襺襼襻觿讘讙躥 

5 躤躣鑮鑭鑯鑱鑳靉顲饟鱨鱮鱭鸋鸍鸐 

6 鸏鸒鸑麡黵鼉齇齸齻齺齹圞灦籯蠼趲 

7 躦釃鑴鑸鑶鑵驠鱴鱳鱱鱵鸔鸓黶鼊 

A 龤灨灥糷虪蠾蠽蠿讞貜躩軉靋顳顴 

B 飌饡馫驤驦驧鬤鸕鸗齈戇欞爧虌躨钂 

C 钀钁驩驨鬮鸙爩虋讟钃鱹麷癵驫鱺鸝 

D 灩灪麤齾齉龘碁銹裏墻恒粧嫺 ╔ ╦ ╗ 

E ╠ ╬ ╣ ╚ ╩ ╝ ╒ ╤ ╕ ╞ ╪ ╡ ╘ ╧ ╛ ╓ 

F ╥ ╖ ╟ ╫ ╢ ╙ ╨ ╜ ║ ═ 

FA 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 

5 

6 

7 

A 

B 

C 

D 

E 

F 


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FB 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 

5 

6 

7 

A 

B 

C 

D 

E 

F 

FC 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 

5 

6 

7 

A 

B 

C 

D 

E 

F 

FD 0 1 2 3 4 5 6 7 8 9 A B C D E F 

4 

5 

6 

7 

A 

B 

C 

D 

E 

F 


Version 1.3 



Appendix F . Font Table - JIS Code 

F-1. Block-1~8 : Non-Kanji Characters, Alphanumeric Characters 


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F-2. Block 16~47 : JIS Kanji Level 1 


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B-3. Block 48~84 : JIS Kanji Level 2 


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RAiO RA8806 - Display Future

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