How to improve the accuracy of Peak Detector as high as posssible

Morning Yatao, 

What you show is an open loop peak detector, you will get much better accuracy with a closed loop peak detector. this is a two amplifier solution where the 2nd stage output, is usually a JFET or CMOS input to reduce hold voltage droop, 

We had produced a hybrid version of that ckt back in the late 80's for radar channels, I am not finding those examples right now, but if no one else comes through, I will look some more. 

From your 200nsec number, I am guessing maybe 10 to 20MHz response speeds. The ones we were doing back in the late 80's were more like 100MHz. So this should be easy 3 decades later. What supplies do you want to use

Incidentally, the output stage I have used before here is the OPA656 JFET device. on +/-5V supplies

Hi Michael,

Good morning!

I thought since OP1 is closed-loop configuration, then why the peak detector is open loop?

The square-wave voltage v=v(t) steps between 0V and 600V and it has a period of 200us. So I guess low-speed ADC can work well here.

How can I predict the accuracy the combination of the peak detector and ADC? And how to choose the accurate peak detector configuration and ADC, OPs' model.

Supplies are flexible for me. That is, depending on the suitable amp and ADC models, I can change the supplies.

Best regards

Yatao

well there are many problems with what you show

1. Imagine you have reached a peak and fallen off from that, the input amplifier goes open loop reducing response time to the next peak

2. The output ampliifer is a buffer to the hold cap, yes, it can be pretty accurate, but that can be improved. 

I would have to look for awhile to come up with those older circuits that I know work, but perhaps current TI folks have something

Dear Michael,

You provide good insights for me.

I'll keep waiting for you and other TI experts for good peak detector.

Best regards

Yatao

Hi Yatao,

you might want to have a look at these threads:

Kai

You will notice these all start out saying they don't work? 

You can perhaps get these to work, and I certainly tried during introduction having been the apps/marketing on these relatively old burrbrown parts, but there might be better ways today. 

Hi Michael,

hhm, I don't understand your first sentence. (These are the moments when I realize that my Englsih is not as good as assumed... :-)

I think you misinterpreted me, but these circuits will work!

In the mid 90s I designed a 1nsec peak detector with the OPA660 (diamond transistor). The application was MIPS detection for a GaAs microstrip detector experiment at CERN. At this time we experimented at the university of Freiburg with GaAs microstrip detectors in the hope to be able to use radiation hard GaAs microstrip detectors in the ATLAS detector of CERN. Unfortunately we could not decrease the supply current of associated GaAs electronics to a sane level. The ATLAS detector runs in vacuum...

Kai

Dear Kai,

    You mean I can choose one configuration from your threads and they can be more accurate than the one I post?

    Dear Kai, in this application, I want to ensure the digitalized results of ADC are as accurate as possible.

     Hence, I wonder, with all the tricks about PCB layout you've taught me, i.e., the shortest track, the intact ground plane, high-speed devices' special layout, etc., can I know the rough precision of the digitalized results prior to the actual experiments? I just mean my posted specific appliction where all data has been given.

Best

Yatao

Hi Yatao,

accuracy very much depends on the shape of input signal here. Please specify as precise as possible the input signal. Showing a scope plot of input signal would also be a good idea :-)

Kai

Well they basically will work, but once you say accurate as possible, not so well. The OPA660 was actually designed in Germany by the BB design center there - I later migrated it to the OPA860

Dear Kai,

The scope waveform is as follows and time axis is 500ns/div.

The shape of v is very close to linear shape except that is has a little curvature.

Note that v rises since 2us with small slope and then rises quickly, with big slope.

Best

Yatao

Yes Kai, this is the better approach, I was having trouble though getting this to hold to the peak voltage yesterday, I always thought it worked better than I am seeing in simuluation right now - I ran your file and it too is more than 10% off the peak in the held value - looks like my diodes might have more reverse leakage than they should - 

Hi Kai,

Sorry for the delay. With your simulations and words, I now have the confidence to use your proposed schematic. When I have to use a circuit that I never used before, I want to consult you. ^.^

But I have two things to ask for your confirmation.

1. The overall input voltage waveform is as the figure below. I need to sense the peak values at every period, i.e., Vpeak1, Vpeak2, Vpeak3 in the figure. Hence, I need to reset the voltage held by C1. If I parallel an analog switch with C1, R3 in your schematic (like the configuration I posted), will the peak detector circuit still work? (I plan to reset the C1 some time before the input edge comes at every period.)

2. Since the input voltage is basically always positive, is it ok to use only positive power supplies for the op amps? I see you use +-9v as supplies. Ohhh, the input voltage rises from 0V to around 5V. Thus, perhaps it is because that THS4631 is not rail-to-rail I/O, then negative supplies are necessary?

I really appreciate your devotion, patience and amazing high level. We really have so much to learn from industry leaders like you and Michael. With your help, we really enjoy using TI products.

Best Regards

Yatao

Hi Michael,

Sorry for this delay.

Thank you for your help in my design. The relative error is 2% with triangle waveform of 1V amplitude. 2% error stands until amplitude rises to 3V. But when I change the amplitude to 4V, the error somehow becomes large, which I guess is because of the input range limitations for the op amps.

I am curious about the use of the diode between the inverting input and output? That is, the SD2 in your schematic and the SD1 in Kai's, are they really necessary?

You are so professional and high level!

Best Regards

Yatao

Good morning,

    Dear Michael.

    Thank you! I'll give it a try the ckt proposed by you.

    BTW, how can you be so experienced and creative in the complicated analog designs? I have found that you are good at every analogcircuit, both high-speed and high performance.

Best regards

Yatao

Well Yatao , 

32 years working in high speed amplifier development groups, contributing to >150 device introductions - part of that was always suitable app ckts to go with the introduction - this particular peak detect I worked on quite a lot in the late 80's. The original showed up in a Comlinear app note circa 1985 using a current feedback input stage and a discrete JFET output stage. 

Dear Kai,

Thank you for your help.

I hope my questions have not brought too much workload for you.

I really respect and admire your high level. You and Michael are really analog design leaders of the highest attainments.

Regards

Best Yatao

Dear Michael,

Thank you for your help all the way.

You are very high level and I will consult you in future analog designs.

Best Regards

Yatao

Thank you for your warm words :-)

Good luck!

Kai